Yield Optimization with EnergyDelay Constraints in LowPower Digital Circuits

1
Yield Optimization with Energy-Delay Constraints
in Low-Power Digital Circuits

• Y. Cao, H. Qin, R. Wang, P. Friedberg,
• A. Vladimirescu, and J. Rabaey
• Berkeley Wireless Research Center,
• University of California, Berkeley

2
Outline

• Motivation
• Impact of parametric variations on yield
• Yield definition and statistical models
• Tradeoffs of Yield, Power, and Timing
• Vdd and Vth tuning
• Transistor sizing
• Yield-Aware Circuit Optimization
• Conclusion

3
Parametric Variations in IC Design
(Figure courtesy of S. Nassif, IBM)

• Process Variations
• Lithography Lgate (15)
• Doping Vth (30), Leff (15)
• Gate oxide Tox (4)
• Metal definition line size (20)

• Circuit Operation
• Power supply Vdd (10)
• Crosstalk noise ?Td / Td (gt50)
• Temperature fluctuation

4
Impact of Variations

• Circuit timing
• Timing specifications have to be pushed further
  and further away from mean value.
• Yield loss occurs otherwise.
• Power consumption
• Extra leakage at standby mode.

• Design methodology
• Traditional worst-case bounded design approach is
  wasteful on resources.
• Redundancies in logic and circuits are necessary
  to ensure correct functionality but they also
  come at expenses.
• Besides speed and power, yield becomes another
  important parameter in circuit design.
• Effective yield-aware design optimization methods
  are needed.

5
Defining Yield Metric For Optimization Analysis

• Yield
• Percentage of registered circuit stages whose
  delays fall within the performance boundary.
• Consistent with normalized variability, which is
  3?/?.
• Reflects design expectation during optimization.

Performance boundary mean delay (110)
6
Circuit Performance Models

• Nominal models Alpha-power law based
• Delay (glogical effort, helectrical effort,
  pparasitic delay)
• Active energy
• Standby energy

7
Circuit Performance Models

• Statistical model Log-normal
• Digital circuits statistical behavior deviates
  from normal distribution especially under low Vdd
  and high Vth.
• Delays above mean value
• spreads wider than those
• below mean value.
• It is due to the non-linear
• delay function

Multiplication central theorem Product of
Gaussian variables approximates log-normal
distribution.
8
Log-Normal vs. Normal
High Vth
Difference in mean value
Medium Vth
Low Vth
0
500
1000
1500
2000
Delay (ps)

• Log-normal behavior is more pronounced under
  low-Vdd and high-Vth operation.
• Applying normal delay model for circuits at low
  (Vdd/Vth) ratio results in error in yield
  analysis.

9
Outline

• Motivation
• Impact of parametric variations
• Yield definition and statistical models
• Tradeoffs of Yield, Power, and Timing
• Vdd and Vth tuning
• Transistor sizing
• Yield-Aware Circuit Optimization
• Conclusion

10
Trade off Yield, Timing, and Power

• Speed and power tradeoff optimization has been
  well studied.
• Now we are up to the stage where
• Traditional worst-case design methodology
• Faces intolerable margin in the presence of
  increasing variations.
• Sacrifices both timing and power.
• Yield concerns limit power reduction.
• Wide delay distribution under low Vdd and high
  Vth, which are key low power design features.
• Yield-aware design methodology is important
  across all levels of VLSI design!

11
Simulation Setup

• Monte-Carlo SPICE simulations of canonical
  circuits inverter chain, NAND chain, and a 4-bit
  adder.

12
Technology Specifications

• A 130nm industrial technology
• First-order variation sources Leff, Vth, and
  Vdd.
• Constant 3?/? is assigned to Vdd (Vth) in Vdd
  (Vth) tuning.
• ? of Vth is correlated to transistor size

13
Vdd and Vth Tuning
Switching Energy
Delay
Total Leakage Energy
Yield
14
Favorable Yield-Power Tradeoffs
10
10
Orders of magnitude
50

• Yield-power tradeoff is favorable for low-power
  designs.
• High-level yield boosting techniques can
  compensate low-level variations, achieving better
  power efficiency.

15
Circuit Sizing Starting with Inverter Chain

• When only considering speed and power trade off
• Tapering factor u is tuned for the optimization

• When yield concern is included
• ?Vth(W, L), the dependence of Vth variation on
  transistor size, is important for yield
  estimation.
• Due to ?Vth(W, L), smaller sized inverter (i.e.,
  larger u) has more severe yield loss (about 5 in
  this case), especially under low Vdd condition.

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Other Design Factors

• This observation relies on the assumption of
  strong correlations among stages.
• Variability with weak and general assumption of
  correlations is another on-going work in the
  group.

• Yield of digital logic circuits is relatively
  insensitive to circuit topology (inverter or
  adder) and logic style (static CMOS or PTL).

17
Outline

• Motivation
• Impact of parametric variations
• Yield definition and statistical models
• Tradeoffs of Yield, Power, and Timing
• Vdd and Vth tuning
• Transistor sizing
• Yield-Aware Circuit Optimization
• Conclusion

18
Yield Sensitivity

• Yield is most sensitive to the ratio of Vdd/Vth.
• Yield increases with larger Vdd, Vdd/Vth, and W.

19
A Design Example
130nm Inverter Chain

• With the same power-timing constraints, yield can
  be improved by increasing Vdd/Vth, with a reduced
  Vdd and larger W.

20
On a System Level Yield-Aware Design Approach

• Bottom-up investigation to bring yield concerns
  across all levels
• Targeting top-down yield-aware design methodology

21
Conclusion

• Circuit yield degrades with power reduction. Thus
  yield is an important concern in low-power
  designs.
• Yield-power tradeoffs are favorable at
  circuit-level.
• Under the same power and timing constraints,
  yield can be enhanced by optimizing Vdd, Vth, and
  sizing together.
• Yield-aware design methodology is need for future
  robust low-power VLSI designs.