OnChip Communication: Architectures and Design Methodologies

1
On-Chip Communication Architectures and Design
Methodologies

• Kanishka Lahiri
• Embedded Systems Design, Automation Test
  Laboratory
• http//esdat.ucsd.edu
• Dept of Electrical Computer Engg, UC San Diego

2
On-Chip Communication An analogy

• Large cities (e.g., Los Angeles), circa 2000
  Reducing commute time by 15 min gt 15b economic
  impact

• Large chips (SoCs), circa 2010 On-chip
  communication will dominate performance, power
  efficiency

3
Talk Outline

• Research Overview
• On-chip Communication Architecture Design
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-Aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Summary and Future Work

4
Research Overview

• System-Level On-Chip Communication
• Design Tools
• Design Methodologies
• New Communication Architectures

5
Talk Outline

• Introduction
• Research Overview
• On-chip Communication Architectures
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Conclusions

6
Technology Trends Global Communication Wires

• Global wires becoming relatively slower
• Gate, local wires obey scaling laws, global wires
  do not

Ho, Mai, Horowitz, The Future of Wires, Proc.
of IEEE, Apr.2001
Increasingly performance limited system-level
communication structures
7
Technology Trends Global Communication Power

• Energy Consumption in DSM Busses
• New sources of power dissipation (cross-coupling)

C.N.Taylor, Y.Zhao, S.Dey, Modeling and
minimization of interconnect energy dissipation
in nanometer technologies, DAC01
Communication structures increasing impact on
system power
8
System-on-Chip Trends

• Flexibility
• Customization of communication architecture now
  possible
• Exploit application/domain characteristics

• Increasing SoC complexity
• Increasing traffic volume diversity
• Inefficient global wires

Design of system-level communication
architectures hold the key to high performance,
low power systems
9
Talk Outline

• Introduction
• Research Overview
• On-chip Communication Architecture
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Summary and Future Work

10
Impact of Communication Architecture on System
Performance
Example TCP/IP Network Interface Cards Checksum
Subsystem
IP CHECK
PACKET QUEUE
CREATE PACK
CHECKSUM
Network
Protocols (Priorities, burst size)
Lajolo, Raghunathan, Dey, Lavagno, Sangiovanni,
CODES98 Lahiri, Raghunathan, Dey, TCAD June 2001
11
Impact of Communication Architecture on Battery
Life
Ex An IEEE 802.11 MAC Processor featuring
Communication Based Power Management (CBPM)
12
Talk Outline

• Introduction
• Research Overview
• On-chip Communication Architecture
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Summary and Future Work

13
Evolution of System Design
T1
T2
T3
T4
T6
T5
I
Computation Mapping
cpu
cpu
ram
ram
udl
dsp
Computation-centric system design - Focus
optimizing computation (e.g., HW/SW
partitioning) - Standard communication
architecture
14
Communication Architecture Design Issues
MPEG decoder
Co-Proc.
CPU1
Comm IF
Comm IF
Video Encoder Interface
Comm IF
Brdg
Appl. Specific logic
Arb1
Mem1
Comm IF
Comm IF
Arbiter2
Arb2
Comm IF
Mem2
Each aspect significantly influences performance
power
15
Overview of Contributions
Topology
Performance Analysis
Power Profiling
Protocols
Mapping
16
Talk Outline

• Introduction
• Research Overview
• On-chip Communication Architecture
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Summary and Future Work

17
System-Level Analysis for Communication
Architecture Design

• Simulation based performance / power analysis
• Expensive, trades accuracy for efficiency
• Not suitable for exploration

18
Performance/Power Analysis Scope
T1
T2
T3
T4
T6
T5
cpu
cpu
ram
ram
udl
dsp
Communication Architecture
19
Analysis Methodology
System Specification
Abstract Communication
HW/SW Partitioning, Component Mapping
Phase I
Co-simulation, power profiling
Timing Inaccurate Execution Trace
Communication bandwidth, power models
Trace Abstraction (SEG Construction)

20
Symbolic Execution Graph (SEG)

• Accuracy
• Capture important timing information
• Capture synchronization, unroll but preserve all
  dependences

21
Communication Architecture Specification
22
SEG Transformations
23
Example SEG Transformation

• SEG Transformations
• Adds new vertices and edges
• Splits communication vertices
• Compute cycles, power for each communication
  vertex
• Calculates timestamps for all vertices
• Shared Bus Architecture (handshaking, priorities,
  burst transfer)

24
Analysis outputs
25
Results Performance Estimation

• Example TCP/IP checksum subsystem

Highly accurate, much more efficient than
complete system simulation
26
Application Efficient Design Space Exploration

• TCP/IP Subsystem under a shared bus architecture

Exploration of 36 communication architectures - 1
second (CPU time)
27
Example IEEE 802.11 MAC Processor
Results Power Profiling
Functional view
28
Experimental Methodology

• IEEE 802.11 MAC processor implemented in POLIS
  co-design environment
• For 5 different HW/SW partitions, evaluate power
  profiles of
• Shared bus architecture, Dual bus architecture

Arch 1
Arch 2
...
Arch 10 IEEE 802.11 MAC Processor
Trace based power profiling

• HW/SW Co-simulation based power profiling
• Instruction level power model for SPARCLite
• HW power estimation ( SIS )
• Analytical bus and memory power models

29
Results Power Profiling

• IEEE 802.11 MAC Processor power profile
  comparison
• HW/SW co-simulation based power profiling
• Trace based analysis tool

1400
HW/SW simulation profile
1200
Trace based profile
1000
800
Power (mW)
600
400
200
0
0
200
400
600
800
1000
time (msec)

• Profiling Error 2.2 (0.5 ms intervals)

30
Design Space Exploration 802.11 MAC
CPU time
Average Power
Power Profiling




Architecture
Trace Based
HW/SW power Co-estm
Trace based
Avg. absolute
Avg. Profiling




Profiling (sec)

Error
()
profiling (mW)
error (mW)
Error ()
(mW)


All HW,

380.7

380.8

0.03

1.8

0.4

0.21

Single bus

418.2

414.9

0.80

4.1

2.2

0.36

All H
W,

Two busses

ICV in SW,

544.2

543.0

0.18

24.0

4.1

0.26

Single bus

596.2

592.9

0.55

13.0

3.4

0.42

ICV in SW,

Two busses

WEP in SW,

613.8

614.0

0.16

45.0

7.3

0.25

Single bus

WEP in SW,

628.3

625.5

0.45

41.8

6.2

0.37

Two busses

517.2

512.2

0.97

19.0

3.2

0.22

FCS in SW,

Single bus

FCS in SW,

590.7

587.4

0.22

4.58

2.2

0.37

Two busses

FCS, ICV in
672.2

672.2

0.00

26.3

3.5

0.26

SW,

Single bus

FCS, ICV in
766.8

763.5

0.43

23.3

4.3

0.42

SW,

Two busses

• Average power error is 0.38 (on average)
• Profiling error (over 0.5 ms intervals) is 3.8
  (on average)
• CPU time 0.31 seconds (on average)

31
Analysis Summary

• System-level analysis framework to drive
  communication architecture design
• Performance Estimation
• Power Profiling (for battery life estimation)
• Accounts for
• Communication Topology
• Communication Protocols
• Communication Mapping
• High Degree of Accuracy
• Comparable to co-simulation based analysis
• Extremely Efficient
• Orders of magnitude faster than simulation based
  approaches
• Can be used iteratively, and for battery life
  estimation

32
Talk Outline

• Introduction
• Research Overview
• On-chip Communication Architecture
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Summary and Future Work

33
Design Space Exploration Framework

• Availability of numerous communication
  templates
• Design decisions
• Communication Mapping
• Protocol Customization
• Design Space Complexity
• Potentially huge
• Large performance variation

34
Design Space Complexity

• n components, k channels
  alternatives for mapping alone!
• Physical constraints restrict design space
  (layout feasibility, bus loading, etc).
• Design space still large

Example system
Template Instance
Bus Controller
C6
C3
C7
C1
bridge
Bus Controller
data
C5
C2
C4
C8
synchronization
8 components, 2 buses, 4 components per bus 70
possible solutions
35
Exploration Methodology
Template Instance

• Profiles inter-component communication
• Clustering-based mapping
• Traffic-driven protocol configuration

Compute Initial Solution
Initial solution
36
Design Space Exploration Results
Example Systems SYS (8 components, 2 buses, 1
bridge), ATM cell forwarding unit (8 ports, 3
memories, 3 buses, 2 bridges)
ATM
SYS
Performance (cycles)
CPU time (seconds)
Speedup
Case
CPU time (seconds)
Speedup
Performance (cycles)
32328
6.8
1.00
shared
10.3
1.00
24654
25593
7.0
1.26
random
11.3
1.61
15314
19998
6.7
1.62
cluster
12.1
2.10
11723
18139
11.8
1.78
23.5
2.67
9242
opt

• Optimizing the communication mapping yields
  large improvements
• Clustering yields 1.3X improvement over random
  mapping
• Further optimization yields 1.65X improvement
  over random mapping
• Exploration methodology is efficient
• Low CPU times, dominated by trace based
  performance analysis step

37
Talk Outline

• Introduction
• Research Overview
• On-chip Communication Architecture
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Summary and Future Work

38
Communication Architecture Tuners
z
MPEG codec
Co-proc
CPU1
Video Enc. I/F
Bridge

Mem1
Appl. Specific logic
Arb1
Arbr2
Mem2

• Time varying communication requirements

Lahiri, Raghunathan, Lakshminarayana, Dey,
Communication Architecture Tuners, DAC 2000
(Best paper award)
39
Inadequacy of Statically Configured Protocol
40
Execution of CAT based Architecture
Pkt. j1 deadline
Pkt. i arrives
Pkt. i deadline
Pkt. j arrives
Pkt. j deadline
Pkt. i1 deadline
Pkt. i1 arrives
Pkt. j1 arrives
CAT-based arch.
i
j 1
i
i 1
j
checksum gt ip_check gt ether_driver
ether_driver gt ip_check gt checksum
All pkts meet deadlines
ether_driver
ip_check
checksum
41
CAT Enhanced SoC Component
COMPONENT
Data control signals
Communication Architecture Interface
To communication architecture
42
Execution of a CAT based Architecture

• Token stream generated by CAT helps CAT classify
  communications
• Variations in control-flow may impose differing
  communication latency requirements
• e.g. cipher state array init
• Partition sequence changes dynamically
• Bus priority changes dynamically
• Latency adapts to requirement

token stream
Comm.
Partition
S2
S3
S0
S1
S0
4
Priority
2
4
Delay
Time
43
Performance Impact of CAT-based Architectures
For each system, CAT based architectures provide
significant improvement
44
Talk Outline

• Introduction
• Research Overview
• On-chip Communication Architecture
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Summary and Future Work

45
Battery Efficient System Design

• Wireless devices becoming increasingly feature
  and function rich

35
400
Battery Gap
30
350
25
300
20
250
Processor power (Watts) (x86 data from Intel)
Energy Density (Wh/kg)
15
200
8 CAGR
10
150
5
100
Li-poly
Li-ion
Ni-MH
Ni-Cd
0
50

• Techniques for designing Battery friendly
  systems
• Include sensitivity of batteries to discharge
  profiles

46
Battery Discharge Characteristics

• Rate Capacity Effects
• Battery efficiency decreases at higher rates of
  discharge

• Well studied in battery modeling literature
• Analytical, electrochemical, circuit based,
  stochastic

Optimizing the power profile can significantly
improve battery efficiency
47
Communication Based Power Management

• Exploits communication architecture to
  dynamically regulate system power profile
• Communication architecture
• Low hardware cost
• System-level visibility
• Dynamic regulation
• Enables run-time trade-offs
• Improves battery efficiency

Lahiri, Raghunathan, Dey, Communication
architecture based power management for
battery efficient system design, DAC 2002.
48
CBPM Operating Example

• Request denied by CBPM policy

49
CBPM Enhanced Arbitration Algorithm

• Components decomposed into MACRO-STATES
• Macro-states are sub-graphs of the CFG
• e.g. WEP_READ_FRAME, WEP_INIT, WEP_ENCRYPT,
  WEP_WRITE
• Specifications are enhanced to generate
  Macro-state transition requests
• Communication architecture keeps track of
• Set of current macro-states
• Set of pending macro-states
• CBPM enhanced architecture grants
  such that

C
S

• Macro-state granularity
• Complexity, flexibility trade-off
• Deadlock prevention circular wait cannot occur

50
CBPM Enhanced Communication Architecture
Standard Bus Protocol (e.g., Static
Priority, TDMA)
MS Power LUT
Fast Adders
MS Priority LUT
Type I requests Represent conventional bus
access requests
Param- eters
Type II requests Represent macro-state
transition requests
MS registers
CBPM Controller
Req4
Gnt4
Shared system bus
51
Impact of CBPM on Battery Life
52
Experimental Methodology

• IEEE 802.11 MAC processor with configurable CBPM
  implemented in Polis environment
• Real 802.11 WLAN traffic used to drive
  simulations

802.11 AP
card
Traffic capture software (Ethereal)
Internet
Server

• Co-simulation for performance estimation and
  power profiling
• Lajolo, Raghunathan, Dey, Lavagno,
  Sangiovanni-Vincentelli, Co-simulation based
  power estimation for System-on-chip design,TVLSI
  June 2002.
• Stochastic modeling of Li-ion battery for battery
  life estimation
• Panigrahi, Chiasserini, Dey, Rao, Lahiri,
  Battery life estimation of mobile embedded
  systems, Intl. Conf. VLSI Design 2001.

53
Results Battery Discharge
No CBPM
Battery state
time (ms)

• Original IEEE 802.11 MAC processor
• Inefficient battery discharge

54
Results Battery/Performance Trade-off

• 1.5 minutes of streaming video (4818 MAC frames)
• 9 CBPM configurations tested

• Improvements in battery efficiency
• Delivered energy up to 1.46x, Lifetime up to
  3.18x
• CBPM enables trade off between battery life and
  performance.

55
Comparison w/other Power Management Techniques

• System Clock Frequency Scaling
• Communication Based Power Management
• Dynamic Power Management

• System clock frequency scaling can lead to
  anomalies
• CBPM benefits are over and above idle shut down
  based DPM
• CBPM results in superior trade-off characteristics

56
Results Hardware Implementation

• Priority based arbiter enhanced with CBPM
  functionality
• Mapped to UMC 0.18um Cu library

Static Priority Bus Protocol
LUT

LUT
Parm
Reg
CBPM

• Area results
• 15104 sq.um
• 56 increase over original arbiter
• Less than 1 overhead at system level
• Delay
• Type II arbitration takes 4 ns Max clock
  frequency 250 Mhz
• Can be improved using multi-cycle arbitration for
  more complex, less frequent CBPM arbitrations

R1
R2
R3
R4
G1
G2
G3
G4
M1
M3
M2
M4
57
CBPM Summary

• Communication Based Power Management
• On-chip communication new knob for regulating
  power consumption
• Methodology for battery efficient system design
• CBPM based architectures
• Enable significant improvements to battery life,
  over and above conventional power management
• Can be statically or dynamically configured to
  trade off performance for battery life

58
Talk Outline

• Introduction
• Research Overview
• On-chip Communication Architecture
• Technology System-Level Trends
• Motivation
• Impact of Communication Architecture on
  Performance and Power
• Communication-aware System Design
• Analysis
• Design Space Exploration
• Adaptive Communication Architecture Design
• Communication Architecture Tuners
• Battery-Efficient System Design
• Communication Based Power Management
• Summary Future Work

59
Summary

• Communication architectures hold an important key
  to performance and power characteristics of
  future SoCs
• Defined systematic approaches to communication
  aware system design
• Described technologies to address various aspects
  of on-chip communication
• New architectures and design methodologies
• Performance analysis and power profiling
• Design space exploration
• CATs Adaptive on-chip communication
• Communication based power management

60
On-Chip Communication Roadmap
COMPUTATION CENTRIC DESIGN
COMMUNICATION AWARE DESIGN
COMMUNICATION CENTRIC DESIGN
Low Standardized, fixed busses (PI Bus, AMBA)
Moderate Customizable archs. (lotterybus, CDMA,
hierarchy, ring)
Advanced On-chip communication networks
Wireless/Optical comm.
Serial Comm. links
Full Digital Signalling (Vdd-GND)
Differential Signaling
61
Publications List

• Journal Articles
• K.Lahiri, A.Raghunathan, S.Dey, "Communication
  Based Power Management", IEEE Design and Test,
  vol.19, no.4, pp. 118-130, July-August 2002.
  (appears in special section with Best of
  Practice papers from DAC 2002).
• K.Lahiri, A.Raghunathan, S.Dey, "System Level
  Performance Analysis for Designing On-Chip
  Communication Architectures", IEEE Trans. on
  Computer Aided-Design of Integrated Circuits and
  Systems, vol. 20, no.6, pp.768-783, June 2001.
• K.Lahiri, A.Raghunathan, S.Dey, "Design of
  High-Performance System-on-Chips using
  Communication Architecture Tuners", submitted to
  IEEE Trans. on Computer Aided-Design of
  Integrated Circuits and Systems, currently under
  review.
• K.Lahiri, A.Raghunathan, S.Dey, System Level
  Power Profiling for battery driven design of
  system-on-chips", submitted to IEEE Trans. on
  Computer Aided-Design of Integrated Circuits and
  Systems, currently under review.
• K.Lahiri, A.Raghunathan, S.Dey, Design Space
  Exploration Strategies for Optimizing On-Chip
  Communication Networks", submitted to IEEE Trans.
  on Computer Aided-Design of Integrated Circuits
  and Systems, currently under review.

62
Publications List

• Conference Publications
• K.Lahiri, A.Raghunathan, S.Dey, "Communication
  Architecture Based Power Management for
  Battery-Efficient System Design", in Proc. Design
  Automation Conf. (DAC) New Orleans, LA, June
  2002.
• K.Lahiri, A.Raghunathan, S.Dey, "Fast System
  Level Power Profiling for Battery Efficient
  System Design", in 11th Symp. HW/SW Codesign
  (CODES) Estes Park, CO, May 2002.
• K.Lahiri, A.Raghunathan, S.Dey, "Battery
  Efficient Architecture for an 802.11 MAC
  Processor", in Proc. Intl.Conf.on Communications
  (ICC), New York, May 2002, pp.669-674
• K.Lahiri, A.Raghunathan, S.Dey, D.Panigrahi,
  "Battery-Driven System Design A New Frontier in
  Low Power Design", in Proc. Intl.Conf. on VLSI
  Design, pp.261-267, Bangalore, India, January
  2002.
• K.Lahiri, A.Raghunathan, G.Lakshminarayana,
  "LOTTERYBUS A New High-Performance Communication
  Architecture for System-on-Chip Designs", in
  Proc. 38th Design Automation Conference,
  pp.15-20, Las Vegas, June 2001.
• D.Panigrahi, C.Chiasserini, S.Dey, R.Rao,
  A.Raghunathan, K.Lahiri, "Battery Life Estimation
  for Mobile Embedded Systems", in Proc. Intl.
  Conf. on VLSI Design, pp.55-63, Bangalore, India,
  January 2001.
• K.Lahiri, A.Raghunathan, S.Dey, "Evaluation of
  the Traffic-Performance Characteristics of
  System-on-Chip Communication Architecutres", in
  Proc. Intl. Conf. on VLSI Design, pp.21-35,
  Bangalore, India, January 2001.
• K.Lahiri, A.Raghunathan, S.Dey, "Efficient
  Exploration of the SoC Communication Architecture
  Design Space", in Proc. IEEE/ACM Intl. Conf. on
  Computer Aided Design, pp.424-430, San Jose,
  California, November 2000.
• K.Lahiri, G.Lakshminarayana, A.Raghunathan,
  S.Dey, "Communication Architecture Tuners A
  Methodology for the Design of High Performance
  Communication Architectures", in Proc. 37th
  Design Automation Conference, pp.513-518, Los
  Angeles, June 2000. (Best Paper Award)
• K.Lahiri, A.Raghunathan, S.Dey, "Performance
  Analysis of Systems with Multi-Channel
  Communication Architectures", in Proc. Intl.
  Conf. on VLSI Design, pp.530-537, Calcutta,
  India, January 2000.
• K.Lahiri, A.Raghunathan, S.Dey,"Fast Performance
  Analysis of Bus-Based System-on-Chip
  Communication Architectures", in Proc. IEEE/ACM
  Intl. Conf. on Computer Aided Design, pp.566-572,
  San Jose, California, November 1999.

63
Communication Platform Selection
Parameterized characterization of communication
traffic
Alternative platforms with known performance
characteristics
ADC
DSP
TDMA bus
MPEG
RAM1
asic
cpu
mpg
DES
CPU
tdma
RAM1
Chain
ASIC
Communication Platform Selection
Ring
Mesh
Etc..
Lahiri, Raghunathan, Dey, Evaluation of the
traffic performance characteristics of on-chip
communication architectures, VLSI Design01
...
...
Static Priority
Hierarchy of buses
64
Other Work

• New architectures
• LOTTERYBUS (Lahiri, Raghunathan, Lakshminarayana,
  DAC 2001)
• CDMA-BUS (Yoshimura et al, ISSCC 2002)
• Characterization of typical communication
  architectures
• Shared Bus, Ring, Hierarchy (Lahiri, Raghunathan,
  Dey, VLSI Design, 2001)
• On-chip traffic characterization for
  applications/domains
• Multimedia (Varatkar, Marculescu, DAC 2002)
• Integrated system task scheduling (computation
  communications)
• Reliability (noise induced errors, soft errors)

65
Experimental Results Efficiency

• Comparison of running time of CAG based analysis
  versus co-simulation

Over 2 orders of magnitude improvement over
co-simulation
66
Case Study Alternative Architectures for TCP/IP
Sub-system
(a) Arch 1 Single shared bus
Arbiter
Single Port memory
67
System Power Profiling and Battery Life
Estimation Methodology
System Specification
Phase II Power and Performance Analysis of basic
computational blocks and communications under
candidate implementations
Phase I HW/SW Co-simulation, Trace Extraction
SEG
System Architecture Definition
LUTs
Phase III SYSTEM POWER PROFILER
Battery Model
Power Profile
Battery life, capacity
68
Phase II Power Delay LUT Construction
Basic Computation Block LUT
Mapping
SPARC 100 Mhz 3.3V
HW 100 Mhz 3.3V
System Tasks Analysis
Basic Comp.Block
B0 WEP_INIT
150mW, 45 us
75 mW, 25 us
Basic Computation Blocks
Communication Events
B1 WEP_KEY
145 mW, 100 us
85 mW, 45 us
B2 CRC_ITER
160 mW, 145 us
160 mW, 24 us
Input stimuli
Simulation based power and performance analysis
Communication Event LUT
Architectural Mappings
Average power, delay estimates
Bus1, M1,S1 66 Mhz, 32 bit, C1uF
Bus 2, M2,S2 33Mhz, 32 bit, C1uF
Communication Event LUT
Basic Computation Block LUT
15uW, 5 us
10 uW, 25 us
15uW, 5 us
15uW, 5 us
69
Phase III Power Profiling

• Communication architecture topology
• Communication protocol parameters (e.g., bus
  priorities)
• Communication Mapping
• Bus Line Capacitances
• Clock frequency
• Mapping of tasks to components
• Component power management modes

SEG
System Architecture Definition
Power and Delay LUTs
Phase III SYSTEM POWER PROFILER
Augmented SEG
70
Battery-Efficient System Design

• For batteries (non-ideal energy sources)
• Lifetime depends on system power profile
• Related Technologies1
• Battery Modeling
• Battery Management and Scheduling
• Battery Efficient Routing and Traffic Shaping
• Battery Efficient System Architecture Design
• Frequency/voltage scaling, task scheduling, power
  management

Battery-efficient system design aims at
maximizing battery life by taking into account
discharge characteristics of the battery
1 K. Lahiri, A.Raghunathan, S.Dey, Battery
Driven System Design A New Frontier in Low Power
Design, Int. Conf. VLSI Design, Jan. 2002.
71
CBPM Design Methodology
Partitioned, Mapped System Spec.
Input Stimuli
Initial Communication Architecture
Macro-state Identification
HW/SW Co-simulation, Power Profiling
Macro- states
System Spec. Enhancement
Macro-state Criticality Analysis
Macro-state Power Profiling
Power Profiles
Execution Traces (SEG)
Modified SEG
Macro-state Power LUT
Macro-state Criticality LUT
System Spec with Type II requests
Performance and Battery Analysis
Configure CBPM Policy
LUTs
Performance, Battery Life, Modified SEG
Implement CBPM in Communication Architecture
yes
no
72
Analysis of Communication Architectures
Communication Architecture Design Space
Topology
Protocols
Mappings
SYSTEM-LEVEL ANALYSIS METHODOLOGY
System Performance
Fast and accurate analysis tools for performance
power
73
Battery Efficient System Design

• Why isnt low power enough ?
• Ideal energy source minimizing energy
  maximizing battery life
• In reality minimizing energy ? maximizing
  battery life

Optimizing the system power profile can
significantly enhance battery efficiency