VLSI Design For Testability Lecture 3.1: Testability

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VLSI Design For TestabilityLecture 3.1
Testability MeasurementLecture 3.2 Automatic
Test Pattern Generation (ATPG) BasicsLecture
3.3 Redundancy Identification and Removal
Instructor Shianling Wu Director,
NE USA, European, Asian Operations SynTest
Technologies, Inc. Fall 2005
Acknowledgement to Contributors V. Agrawal
(Auburn Univ), M. Bushnell (Rutgers Univ), X,
Chen (CCNY), C. Stroud (Auburn Univ.)
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• Testability Measures
• Automatic Test Pattern Generation (ATPG) Basic
• Redundant Fault Removal

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Testability Measurement
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Iteration 2 Combinational (0) with Clocks
CC0(Q)CC0(D)CC0(clk)CC1(clk)
14
15
9
9
9
5
5
6
5
Iteration 2 Sequential (0)
SC0(Q)SC0(D)SC0(clk)SC1(clk)1
14
1
15
9
1
1
9
9
1
1
5
5
6
1
1
1