BASEBAND AND DIGITAL RECEIVER SYSTEMS OF THE GMRT

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BASEBAND AND DIGITAL RECEIVER SYSTEMS OF THE
GMRT

• B. Ajith Kumar
• Group Co-ordinator Back-end Systems

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(No Transcript)
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Radio Telescope ReceiverAn Introduction
4
A Single Dish Radio Telescope

• Collects radio waves from the celestial sky over
  an effective aperture area and converts the
  signal to an electrical voltage, in 2 orthogonal
  polarisations.
• A Highly sensitive Receiver with Low Noise
  Amplifiers provide a total Gain (approx) 100 dB.
• Power detectors are used to measure the power in
  the amplified signal and it is integrated to
  achieve the desired signal-to-noise ratio.
• Final sensitivity depends on Collecting Area,
  Bandwidth, Integration Time Receiver Noise
  Temperature.

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A Single Dish Radio Telescope

• For High Sensitivity Signal-to-Noise Ratio
  Collecting Area HIGH,
• 
  Bandwidth -
  LARGE,
• 
  Integration Time-
  LARGE,
• 
  Receiver Noise -
  LOW.
• Map of the Source Structure is made by multiple
  pointings over different parts of the source.
• Celestial Radio signals are VERY weak unit of
  flux used is
• 1 Jansky 10 26 W / m2 / Hz
• Input radio power into a typical telescope is
  -100 dBm !
• (would take 1000 years of continuous
  operation to collect 1 milliJoule of energy !!)

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Single Dish Array Telescopes

• Resolution and sensitivity depend on the physical
  size (aperture) of the radio telescope.
• Due to practical limits, fully steerable single
  dishes of more than 100 m diameter are very
  difficult to build.
• ? resolution (? / D) 0.5 degree at 1
  metre (very poor compared to optical
  telescopes).
• To synthesize Telescopes of larger size, many
  individual dishes spread out over a large area on
  the Earth are used.
• Signals from such array telescopes are combined
  and processed in a particular fashion to generate
  a map of the source structure EARTH ROTATION
  APERTURE SYNTHESIS
• ? resolution ? / Ds , Ds largest
  separation.

New 100-m Greenbank Telescope
The Very Large Array
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Radio Interferometry Aperture Synthesis

• Signals from a pair of antennas are
  cross-correlated (cross-spectrum is obtained).
• This functions like a Youngs double slit,
  measures one Fourier component of the image in
  the U,V Plane.

• From measurements using different pairs of
  antennas, several Fourier components of
  the image are obtained.
• Inverse Fourier transform of the combined
  visibilities gives a reconstruction of the
  original image ? aperture synthesis.

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GMRT Receiver - Existing SystemBaseband
Digital Receivers
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Baseband Digital Receivers

• Generate Intermediate Freq-uency (IF) signals at
  Dish base for transportation to Central
  Electronics Building (CEB) through OF cables.
• Down convert Bandshape the IF signals at CEB to
  facilitate the digitisation.
• Processing of signals in digital domain to
  generate Correlator data and record them.
• Generate and distribute coherent Local Oscillator
  signals for all Frequency Conversions.

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Baseband Digital Receiver Systems

• Analog IF Receiver circuits at the Antenna site.
• Baseband Receiver circuits at the Central Station
  (CEB).
• Local Oscillator circuits Phase locked to a
  Master Ref.
• Digital Back-ends for Interferometry Pulsar
  Observations.

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Analog Receiver at Antenna

• The Analog Receiver systems at the antenna
  converts the RF signal in both polarisations to a
  common IF Frequency of 70 MHz.
• SAW (Surface Acoustic Wave) Filters are used at
  70 MHz for Band shaping of the signals.
• The IF signals are then upconverted to 130 and
  175 MHz for transportation to CEB through Optical
  Fiber.
• High dynamic range ALC circuits are used before
  the signal is given to OF Transmitter to maintain
  a constant power.

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Analog Receiver at Antenna

• Choice of three IF bandwidths 6, 16, 32 MHz.
  Bandwidth compensation circuits to provide
  constant power irrespective of selected
  bandwidth.
• Variable pre-attenuator values in the range 0 to
  30 dB in 2 dB steps.
• Variable post-attenuator values in range 0 to
  30 dB in 0.5 dB steps.
• Automatic Level Control (ALC) circuits with
  dynamic range 30 dB and 1.0 sec time constant
  with facility to switch off for specific
  observations.
• Overall gain of 60 dB (approx) in IF chain with
  linearity upto 5 dBm at output (in ALC off mode).

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IF System Response
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Analog Receiver at Antenna - Main Plug in Units
70 to 130/175 MHz Converter
RF to 70 MHz Converter
Monitor Unit
Control Unit
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Baseband Receiver at CEB

• Converts IF Frequency signals to two sidebands
  each of 0 to 16 MHz) with high Image Rejection.
• 8th order Butterworth Filters for Bandshaping of
  the sideband signals.
• Facility to choose different observaion bands in
  the two IF channels.
• ALC circuits are used before the signal is given
  to Sampler in the ADC cards to maintain a
  constant power.

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Baseband Receiver at CEB

• Choice of nine BB bandwidths 65 KHz to 16 Mhz
  in octave steps for each sideband. Bandwidth
  compensation circuits to provide constant power
  (0dBm) irrespective of selected bandwidth.
• Variable gain amplifier circuits to vary the gain
  in system from 0 to 24 dB in 0.5 dB steps.
• Automatic Level Control (ALC) circuits with
  dynamic range 8 dB and 1.0 sec time constant with
  facility to switch off for specific observations.
• Overall gain of 50 dB (approx) in BB chain with
  linearity upto 10 dBm at output (in ALC off
  mode).
• Local Oscillator for Baseband Conversion
• DDS based Synthesisers 50 to 90 Mhz, Step 100
  Hz.
• Spurious lt -60 dBc, Phase Noise , -80 dBc/Hz at 1
  KHz.

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BB System Response
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Baseband Receiver at CEB - Main Plug in Units
IF to BB Converter
BB Filter ALC
BB Control Monitor
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Spectrum at FE, IF, BB, Corr-self Outputs
FE
CORR
BB
IF
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Gain Distribution in Analog System
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Local Oscillator Generation System

• A 5 MHz Rubidium Frequency Standard at CEB is
  used as the Master Reference.
• LO Ref circuits at CEB generate the 105 and 200
  MHz reference signals which is sent to antenna.
• At antenna site LO Synth circuits generate LO
  frequency in 100 to 1500 MHz range from the
  reference signals.
• Fourth LO circuits at CEB generate the LO for IF
  to BB conversion.

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LO Master Reference System at CEB
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LO Master Features

• Uses a GPS disciplined Rubidium Standard as the
  Main Time and Frequency Standard.
• Reference signals generated from the standard are
  send to antenna locations for generating coherent
  LO signals.
• Generates LO signals for Frequency conversions in
  CEB electronics.

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TM-4 GPS Receiver Features

• High performance OCXO - 10 MHz
• Phase Nose lt -124 dBc/Hz (10Hz)
• Spurious lt -70 dBc,
• Harmonics lt -50 dBc
• Short Term Stability lt 1 X 10-11 (1Sec),
• Long Term Stability lt 1 X 1012 (24Hrs)
• Accuracy of 1pps 1nS

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Rubidium Standard Features

• Output 10 MHz, Sinewave
• Phase Noise -137 dBc/Hz at 10 Hz, Spurious lt
  -130 dBc,
• Harmonic lt -25 dBc
• Short Term Stability lt 2 X 10-12 (100S),
• Long Term Stability lt 5 X 1011 (monthly)

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LO Reference Regeneration at Antenna Site
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LO-Ref Regeneration

• Transistorised VCXO with Operating Frequency
  of 105 MHz and 200 Mhz in a Phase Locked Loop
  (PLL) configuration with Loop BW 70 Hz.

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LO Synthesiser System at Antenna Site
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LO Synth Features

• Freq Coverage 100 to 1500 MHz
• Step Size 1 MHz ( lt 350 M )
• 5 MHz ( gt 350 M )
• Power Output 11 dBm /- 3dB
• Spurious Level lt -60 dBc
• Harmonic Level lt -20 dBc
• Phase Noise lt -60 dBc/Hz
• 10 KHz Offset
• Phase Jitter 0.1 mS
• Line Freq Mod lt -20 dBc

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Digital Receiver at CEB

• The Digital Receiver supports two modes of
  operation
• The Earth Rotation Aperture Synthesis
  Interferometry
• The Phased Array Mode Pulsar Observations

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Digital Receiver at CEB

• The Synthesis Mode
• Useful for making maps of extended radio sources.
• Each antenna pair used as an interferometer that
  measures one Fourier component of the radio image
  ? (3029)/2 435 instantaneous Fourier
  components.
• Rotation of the Earth is used to get more Fourier
  components (UV plane).
• Array configuration optimized to give maximum,
  uniform coverage in the Fourier domain.
• Final image obtained by 2-D inverse Fourier
  Transform of recorded data.

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Digital Receiver at CEB

• Both Back-ends (FX Correlator Pulsar Receiver)
  can operate simultaneously.
• Common signal processing stages ADC, Delay
  correction, Fringe stopping and FFT.

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Features of the ADC Section

• Clock Rate 32 Msamples/Sec.
• No. of bits 8 bits (only 6 msb bits used).
• Analog Input Voltage /-1 Vpp.
• Input Power Level 0 dBm.
• Output Logic Levels ECL Level.
• ADC chip used AD9058 Flash type ADC

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ADC Circuit
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Delay Section

• Max Delay of 2.048 mS (in units of 32 ns).
  Dynamic update in 2 Sec.
• Noise switching Walsh demodulation. RFI
  mitigation in time domain.
• Conversion of unsigned 6 bits from ADC to 4 bits
  sign magnitude form.
• Dual clock support to take care of extra overhead
  cycles in the FFT.
• Narrow bandwidth support for spectral line mode
  of observation, using the decimation technique
  (de-sampling) on the sampled data.
• Bandwidths supported 125 KHz - 16 MHz of analog
  Baseband signal.
• Channel multiplexing at the output (as needed
  for the full polar mode).
• The hardware implemented using two Altera FPGA
  devices per antenna (all 4 channels) on one
  board, and PLDs for bus arbitration logics.

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Delay Section
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FFT Section

• ASICs are used as basic building block for FFT
  operation, each operates at 32.25 MHz clock
  speed. This is different from 32 MHz sampling
  clock, mainly to accommodate the extra four
  overhead clock cycles consumed by FFT operation.
• The FFT operation is pipelined and uses Divide
  and Conquer Approach algorithm to compute a 512
  point FFT. Five ASICs per pipeline are used to
  calculate the 512 point FFT operation, with the
  operations split as radix 2, 4, 4, 4 4
  computations.
• Online Fringe Stopping and Fractional sample time
  correction.
• Input 4 bits, sign magnitude format.
• Output 4 bits real, 4 bits imaginary and
  4 bits of common exponent.
• The Output from two polarisations of same
  sideband is time multiplexed.

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FFT Circuit
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FX Correlator at CEB

• Computes the Cross Self spectra for each
  antenna in real time using ASIC.
• Input data rate 1.9 GS/s.
• Output visibilities integrated 8192 times to a
  time resolution of 128 ms.
• Supports sub-array mode of GMRT with different
  sources / frequencies for each sub-array.
• Total compute power 100GCops
• Uses mostly ASICs some FPGAs.

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Main Features of the MAC Sub-system

• MAC sub-system Multiplies and Accumulates the
  signals from each pair of antennas.
• Provides a 30x30 matrix for each of 2 sidebands
  2 polarisations, with 256 spectral channels per
  sideband.
• Visibilities are output at the rate of once every
  128 ms.
• Number of spectral channels is
• 128 in 32 MHz BW, Indian Polar,
• 128 in 16 MHz BW, Full Polar,
• 256 in 16 MHz BW, Non-polar.

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The ASIC in MAC mode

• Each ASIC takes input from 2 FFT cards, 12 bits
  each.
• The inputs go to registers and they get
  multiplied and then accumulated for the N number
  of FFT cycles.
• The accumulated data of one cycle is stored in
  the first bank of the ASIC RAM, which is 256 36
  ( of spectral channels Bits in output
  15,15,6). In the next cycle, MAC operation uses
  the second bank of the ASIC RAM.
• During the four dead cycles, the Data goes to the
  acquisition machine through back plane and DAS
  card.

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MAC Card Layout

• Each MAC card accepts inputs from 8 FFT cards.
  Four column inputs and Four row inputs.
• The 16 ASICs compute the basic 4x4 MAC matrix
• The inputs to each ASIC are in 4,4,4 format the
  output is in 15,15,6 format
• All ASIC outputs are connected to a common bus
• Total of input signals/card 8 12 2 (
  of FFT of o/p bits/FFT ECL form of each
  bit) 192
• Total output signals/sideband 192 11 3 (
  of signals/MAC card of cards/FX rack of
  FX racks/sideband) 6336

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MAC Card
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System Parameters for the GMRT (in
Synthesis Mode)
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Pulsar Receiver at CEB

• Delay and phase corrected data from the FFT
  outputs is given to the GMRT Array Combiner (GAC)
• The GAC allows any user selected set of antenna
  signals to be added to get the array output.
• Simultaneous operation in two modes possible -
• IA - Incoherent Array (power sum)
• PA - Phased Array (voltage sum)
• Simultaneous multi-frequency observations ---
  trade-off BW for different sub-arrays.

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Pulsar Receiver - Features

• The GMRT Pulsar Receiver provides high time
  resolution, single dish output by suitably
  adding the signals from individual antennas of
  the GMRT.
• User selectable gains can by applied to the
  signals passing through the GAC, for individual
  spectral channels in each polarisation.
• The output of the GAC is at the raw rate of 16
  microsec per sample, with 256 spectral channels
  present per 16 MHz bandwidth, per polarization.
• It uses the ADSP 21020 as the main processing
  unit, along with a mix of PLDs and FPGAs for
  control and computation.
• Both the modes (Incoherent Array Phased Array)
  are fully operational for both LSB and USB parts
  of the Digital Backends, hence can be used for
  full Bandwidth ( 32 MHz) operation.
• The entire pulsar receiver can be configured and
  controlled from a GUI that can be run from a
  Linux machine in the Main Control Room.

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Block Schematic of Pulsar Receiver
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IA PA Pulsar Receiver

• These two back-ends allow the raw data stream
  from the GAC to be integrated in time / frequency
  to achieve a net data rate at which the signals
  can be recorded using PC based data acquisition
  systems.
• In addition, the PA bin computes the basic self
  and cross terms between the voltage signals of
  the two polarizations, from which the full
  Stokes parameters can be constructed.
• The highest time resolution achievable is 128
  microsec for the IA mode and 512 microsec for
  the full Stokes PA mode.
• These back-ends are available only for one
  sideband (16 MHz) BW and are connected to the
  upper sideband (USB).

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Polarimeter

• Like the IA and PA Receivers, it takes in the raw
  data from the IA and PA outputs of the GAC and
  further processes them in Time/Frequency before
  recording on PC based DAQ systems.
• Uses Altera FPGA ( FLEX 10k100 ) for the
  computation of four stokes parameters and
  implementation of the signal flow logic for
  different modes of observations like IA PA.
• The highest time resolution achievable at present
  is 64 microsec for the IA mode and 256 microsec
  for the full Stokes PA mode.
• Is available for both LSB and USB, Provides full
  polar mode phased array data.

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System parameters for the GMRT (in Array
Mode)

• Effective Area 30,000 sq. m. for 610
  MHz and below
• 20,000 sq.
  m. for 900-1400 MHz
• Maximum Bandwidth 32 MHz
• Sampling time gt 16 microsec for
  Incoherent Dedispersion
• lt 1
  microsec for Coherent Dedispersion
• Polarization All 4 Stokes parameters for
  Coherent Phased Array
• Total intensity for
  Incoherent Array
• Sensitivity
• For single pulse mode (using PA) Sav
  35 mJy
• For pulsar search mode (using IA) Sav 1
  mJy
• Freq 325 MHz all 30 dishes added 2 Pol
• 100 uS sampling 10 minute scans

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System Failure Summary Spares

• Total No. of Problems in 2007 1777
• Antenna Base Electronics 4.5
• Baseband Electronics 1.0
• LO System 3.5
• Digital Back-ends 17.5
• Working Spare Availability 3 set each
• Average Service Time for Faults lt 1 Hr

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GMRT Baseband Digital ReceiversRecent
Modifications XI Plan Upgrades
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• Software Back-end
• 30 to 1 Power Level monitoring System
• 100 MHz Backend for tests with Broadband signal
• System Upgrades XI Plan

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Software Back-end

• Real-time correlation for 30 antennas, 2 pols, 16
  MHz band.
• 4 bit Raw voltage recording 30 antennas, 2 pols,
  16 MHz band.
• Modes of Operation
• Real-time data acquisition writing to disks,
  off-line read-back of recorded data and
  computation
• Real-time Data Acquisition computation.

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Software Back-end - Operation

• Run synchronous sampling on 8 ADC boards (32
  antennas) 16/32 MHz BW.
• Transfer data from ADC board to CPU unit (via
  interrupt driven DMA) in large blocks (32 MB
  block size --gt 8 MB per antenna).
• For recording mode, synchronous write to disk
  locally at each node.
• For correlations, distribute data from all
  antennas (using time division multiplexing) to
  all nodes -- each node handles 1/8 time slice
  from each block.
• Carry out Delay correction, FFT, Fringe stop, MAC
  and other required operations at each node.
• Record integrated visibilities results to local
  disk on each node, or send them to collector
  nodes.

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Software Back-end Current Implementation

• Layer 1 ACQ Nodes Dual core, Dual processor
  Intel Xeon CPUs, 1 GB RAM, Dual Gigabit Ethernet
  ports, 8-bit, 4 Channel, 100 MSPS, PCI-X
  compliant ADC card
• Layer 2 Compute Nodes Quad core, Dual
  processor Intel Xeon CPUs, 2 GB RAM, Dual Gigabit
  Ethernet ports, 2 TB storage capacity
• Layer 3 Recording Nodes Dual core, Dual
  processor Intel Xeon CPUs, 2 GB RAM, Dual Gigabit
  Ethernet ports, 2 TB storage capacity
• This results into total No of Nodes required 48

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Software Back-end - Features

• More Dynamic range --gt More bits per sample
  -- for better protection against Radio
  Frequency Interference (RFI).
• Better Frequency Resolution for Full Bandwidth
  --gt Longer FFT lengths.
• Ability to filter out impulsive RFI and
  Power-line RFI from raw data, visibility data.
• Ability to record raw data from each antenna
  and play back with different options.
• Ability to form multiple beams within the
  primary beam (in Phased Array mode).
• Ability to modify, add new sophisticated
  algorithms with ease.

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Software Back-end Systems
Front Side
Rear Side
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Software Back-end Systems
ADC Card
DAQ PC
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Hardware Software Backend Comparison
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Hardware Software Backend Comparison
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First Image

• Image made from S/W back-end (by J. Chengalur)
• Source 3C286
• Frequency 1280 MHz
• Bandwidth 16 MHz
• Time 20 mins data

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New IF Conversion for Software Back-end

• Interface the Software Correlator to the current
  GMRT Receiver.
• Facilitates Simultaneous use of both Software and
  current Correlator Back-ends.
• Provides Analog signals at 32 MHz BW to the ADCs.
• Facility to inject a noise signal to Baseband and
  SW Correlator for easy trouble shooting.

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New IF Conversion for SW Back-end
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LO Generation for New IF Conversion

• Harley CTI make DDS units used for generation
  of LO signals.
• Freq 100 1600 MHz
• Freq Step 1 MHz
• Ref Signal 10 MHz
• Facilitates shifting the IF signal to any value
  less than 100 MHz.

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New 30 to 1 program

• 30 to 1 sytem is used for monitoring the IF
  signals at CEB.
• New 30 to 1 program based on Labview is Ready.
• Switch selection through NI DAQ and Instrument
  control through GPIB.
• Works in Windows and Linux platforms.
• Limitations on the PC clock speed and processor
  removed.

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Existing 30 to 1 System
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• Two quadrature phase signals of 50 MHz BW each is
  generated from incoming L-band signal.
• Broadband Quadrature Hybrid is used to generate
  the LO signals at 90 deg phase.
• Quadrature Sampling, Digit-isation, Signal
  Conditioning and Correlation (FX) to be
  imple-mented on composite Serendip-V boards.
• These Back-ends will be used for the 15 mtr dish
  Receiver also.

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Analog Circuits - Status

• Status Circuit Design completed, Components
  ordered.
• Schedule Two antenna system expected to be
  ready in three months time.
• Estimated cost US 300 (2 ant)

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Quadrature Hybrid

• Pulsar Microwave
• Model QSA-09-464/6
• Frequency Range
• 400 to 2000 MHz.
• Amplitude Balance 1 dB
• Phase Balance 6 deg.

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Digital Circuits

• Serendip-V boards will be used as the Digital
  Back-ends for the first prototypes. We have a
  Serendip System with two Boards available with
  us.
• These Boards are General Purpose Digital boards
  with in-built ADCs and FPGA processors suitable
  for various applications.
• Serendip Boards are in use in various Telescopes
  for Digital Back-end processing.

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Serendip Board Schematic

• Four ADCs 8-bit ADCs with 128 MHz analog BW.
• Provision for two 100 MHz in-phase
  quadrature-phase Analog signals.
• Xilinx Virtex-II 6000 (XC2V6000) can be
  dynamically programmed for Signal Processing.
• Xilinx Virtex-II 1000 (XC2V1000) as a
  reconfigurable backend processor to pass data to
  an independent computer
• 200 digital I/O lines 256 MB DRAM.

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SERENDIP-V Setup
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Serendip - V System
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Self-Correlation Ch-A(Noise Signal 10MHz BW)
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XI Plan Upgrade Scheme

• One stage of Frequency Conversion for all
  frequencies above 800 Mhz.
• Direct Sampling and digitisation these signals
  using ADCs operating at a clock rate of 1600 Mhz.
• Digital filter bank to separate the signals into
  eight bands of 100 Mhz bandwidth each.
• Any four of the above filter outputs can be
  selected for correlation.

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Features Comparison with Current System

• Upgraded System
• Seamless Coverage from 50 to 1500 MHz.
• Supports instantaneous Bandwidth of 400 MHz in
  each polarisation.
• Facility for multi-frequency observations 100
  MHz band widths at four different bands.
• Integrated Power Level Monitoring Circuits for
  easy trouble shooting.

• Current system
• Supports Seamless coverage in 50 to 1500 Mhz,
  with a few blind spots in this range.
• Instantaneous Bandwidth of 32 MHz in each
  polarisation.
• Facility for dual frequency observations with 32
  Mhz in each band.
• Power Level monitoring available at few stages in
  Receiver chain.

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• Convert L-band signal from antennas to 100-900
  MHz range with 1 stage conversion
• The signals are digitised using high speed iADC
  Boards at a clock rate of 1000MHz.
• Digital Filters used to split the signal to 100
  MHz bands.
• Signal conditioning and Correlators to be
  implemented in iBOB boards.
• High-end FPGA Boards like BEE2, Roach Boards to
  be used in final system.

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iADC Boards

• Digitise 2 Analog channels
• Sampling rate
• 1 Gsps 2 Channels
• or 2 Gsps 1 Channel
• ADC used
• Atmel AT84AD001B
• 8-bit, 1 GSps dual ADC
• Analog BW 1500 MHz

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iBOB Boards

• Uses a Xilinx XC2VP50 FPGA as the main compute
  resource, suitable upto a four ant Back-end.
• Allows input data streams to be packetised for 10
  Gbit, infiniband transmission to High end FPGA
  Back-ends like BEE2 boards
• For Final 30 ant System we need to go for a
  High-end FPGA Backend Like BEE2 or Roach.

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iBOB Boards with Two iADCs
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BEE2 Boards

• The BEE2 integrates high computational density
  with high speed I/Os
• Has 5 nos of XC2VP70 Virtex-II Pro FPGAs (4
  user 1 control), each capable of 48
  billion MAC (16 bit) operations 10x a P-5
• 4 GB of DDR2-SDRAM memory, aggregating 12.8 GBps
  throughput from each user FPGA
• 10 Gbps InfiniBand links from each user FPGA
  total of 18 per board 2 Power PC cores.
• Power budget 250 W per board

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BEE2 Board
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XI Plan Upgrade Status

• Analog Processing Circuits Prototype Design
  Ready, Hardware to be implemented, Order placed
  for components.
• iADC iBOB Boards Order placed for eight
  boards (expected in Apr 08). Currently exploring
  possibility of fabricating 8 boards locally.
• High-end FPGA Back-ends BEE2 / ROACH Boards to be
  ordered.
• Price iADC - US 1300, (one ant, two channels)
• iBOB - US 1800, (two ant, two
  channels)
• BEE2 - US 8000

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Thank You