Investigation of StrainTemperature Stress on Rapid Thermal Ultrathin Gate Oxide - PowerPoint PPT Presentation

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Investigation of StrainTemperature Stress on Rapid Thermal Ultrathin Gate Oxide

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... densities, thermal effects become significant in increasing numbers of designs. ... cool down and make in situ measurement. 4 ... – PowerPoint PPT presentation

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Title: Investigation of StrainTemperature Stress on Rapid Thermal Ultrathin Gate Oxide


1
  • Investigation of Strain-Temperature Stress on
    Rapid Thermal Ultra-thin Gate Oxide

Student Chia-Wei Tung ??? Advisor Jenn-Gwo Hwu
??? ??
Investigation of Strain-Temperature Stress on
Rapid Thermal Ultra-thin Gate Oxide
2
  • As the IC technology advanced toward ever-smaller
    geometry, this oxide layer has also been scaled
    down in thickness to keep the performance of the
    transistor from degrading.
  • However, as technology downscaling causes greater
    power and package densities, thermal effects
    become significant in increasing numbers of
    designs.
  • With the wafer size from 6inch to 8inch or
    12inch, wafer cutting become more inevitable in
    the upper stream package and testing foundries.

Investigation of Strain-Temperature Stress on
Rapid Thermal Ultra-thin Gate Oxide
3
Dynamic scheme for applying strain-temperature
stress
100oC 30sec
Quartz holder
cool down and make in situ measurement
Investigation of Strain-Temperature Stress on
Rapid Thermal Ultra-thin Gate Oxide
4
Part 1 - In the form of a full wafer
Part 2 - In the form of a strip
  • It is found that the ultra-thin gate oxides in
    the form of a strip treated thermal stress have
    larger current variation. However, the
    tensile-temperature stress samples remain the
    best properties than compressive-temperature and
    control samples.
  • We found that the electrical pre-measurement will
    cause the leakage current on accumulation region
    increases, this phenomenon isnt occurred on the
    samples without scribing.
  • To explain the phenomenon of electrical measuring
    influence, we suggest that electrons after
    electrical measuring are trapped at hidden trap
    precursors in SiO2 bulk then be activated when
    temperature stress so that percolation path is
    induced.
  • Various strain-temperature stresses are
    demonstrated for studying the reliabilities on
    MOS capacitors, and the experiment results show
    that the tensile-temperature stressed oxides
    exhibit lower saturation current variation and
    improved breakdown endurance.
  • The reason that we propose for advantages of
    tensile-temperature stress is that the defects
    and interface traps at the interfaces between
    SiO2 and Si are much better than the others.

Investigation of Strain-Temperature Stress on
Rapid Thermal Ultra-thin Gate Oxide
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