Wolfgang Nebel, Domenik Helms, Eike Schmidt, Milan Schulte, Ansgar Stammermann

1
Low Power Design for SoCs

• Wolfgang Nebel, Domenik Helms, Eike Schmidt,
  Milan Schulte, Ansgar Stammermann
• This work has been partly funded by the CEC under
  contract IST--2000-30125

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Outline

• Why Low Power?
• What is Needed for Low Power?
• Low Power at Specification Level
• Low Power at Architecture Level
• Summary

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Power Driver Speed
Source Intel
4
Power Limit Energy Density
Source adapted from Intel
5
Design Cost Challenge System Level
Design cost 8 M. Gate ASIC
342,417,579
15,066,373
Source ITRS
6
Impact of System Architecture
Source R. Newton - UCB
7
Less Time to Lower Power ?
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System Level Power Optimization

• To Do List for Power Optimization
• Algorithm selection
• Identification of hot spots
• Algorithm optimization
• Power optimized system partitioning
• Power optimized memory architecture
• Power optimized resource sharing / allocation
• Power optimized resource selection
• Power optimized data encoding
• Power optimized floorplanning

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SoC Power Optimization Requirements

• Demand for
• Impact analysis of design decisions
• Reliable estimation of power consumption
• Fast analysis results
• High relative accuracy
• Link to technology
• This requires to
• Predict Logical Architecture
• Predict Physical Architecture
• Estimate Power Consumption

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SoC Power Analysis Design Flow
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Algorithm SelectionJPEG Decompression
Accurate Algorithm
Fast Algorithm
Picture Quality
99
better
388.4 µWs
402.7 µWs
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Identification of Hot Spots
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Memory MappingWavelet Transform (1D)
10.9 ?Ws
12.1
19.2
intra array optimization
inter array optimization
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Design Flow
modified
original
Specification
if (c2) A A ltlt 1 else while (cgt1)
A A c c--
while (cgt1) A A c c--
Which algorithm is the best?
Algorithm Selection Algorithm Transformation
Algorithm
Which architecture is the best?
Resource Sharing Scheduling Module
Selection Floorplan
Architecture
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Impact of Binding
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
1 1 0 0
1 1 0 0
2 x 2 transitions
2 x 2 transitions
2
1
1
2
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 1 0 1 1 0 1 0
0 1 0 1 1 0 1 0
1 x 2 transitions
6 x 2 transitions
ADD
ADD
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Resource Sharing / Allocation

• How many adders should I spend in my design?

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Impact of Low Power Binding

• FDCT synthesized with Synopsys
• Gate-level power estimation
• with and w/o power optimization
• more than 50 difference between best and worst
  binding

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Data Encoding
20 power gain
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Component Selection
EFR Vocoder
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Summary

• Specification level impact analysis.
• First time right architecture.
• Up to 75 power reduction in minutes.
• Avoids design iteration down to RT or gates.
• Saves up to months of design time.