Physically Aware Data Communication Optimization for Hardware Synthesis

1
Physically Aware Data Communication Optimization
for Hardware Synthesis
Adam Kaplan, Philip Brisk and Majid Sarrafzadeh
Computer Science Department University of
California, Los Angeles

• Ryan Kastner, Wenrui Gong,
• Xin Hao, Forrest Brewer
• Dept. of Electrical and
• Computer Engineering
• University of California,
• Santa Barbara

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Hardware Compilation
Application specified in high level language
HDL (behavioral, structural)
Compiler

• We focus our efforts on mapping an application
  written in a high-level language to a hardware
  description
• We desire this mapping to have optimal
  characteristics (area, latency, etc.)
• In this talk, we focus on the problem of
  minimizing data communication in the final
  hardware

Synthesis and Physical Design
Chip, bitstream,
3
Obligatory Design Flow Slide
4
Characterizing Data Communication

• Examples of data communication schemes

Control Node 1
Memory (Register Bank, RAM)
Control Node 1
Bus
Control Node 3
Control Node 2
Control Node 2
Control Node 3
Control Node 4
Control Node 4
Distributed
Centralized
Data communication wire
Data communication memory access
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Identifying Data Communication

• Determine relationship between place(s) where
  data is defined and where data is used

a ?
b ?

• Naïve method all use-points of a variable
  depend on all definitions of that variable
• Not all use points use a variable

a ?
b ?
a ?
c ?
? b
? c
? a
Need analysis to minimize the amount of data
communication
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Use of SSA in Compilation

• Must determine relationship between where data is
  generated and where data is used
• Problem formulations
• DAC02 Minimize the total number of bits
  communicated between all pairs of control nodes
• Today Minimize overall wirelength
• SSA (Static Single Assignment)
• Changes each variable to have a unique definition
  point
• Must add ?-nodes to merge definitions

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Physically Aware Compiler Transforms

• Consider layout information during compilation
• Modify transforms to consider physical info
• Ideal full physical synthesis extremely
  accurate, but way too time consuming

• Approximate using floorplanning
• Much faster
• Gives good enough high level physical picture

application
Hardware Compilation

• Previous data communication work
• No physical information
• Can lead to negative results

Physical Synthesis
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Physically Aware Data Communication

• Modify placement of F-functions to consider
  wirelength

?-Placement Algorithm

• Given a CFG Gcfg(Vcfg, Ecfg)
• perform_ssa(Gcfg)
• calculate_def_use_chains(Gcfg)
• remove_back_edges(Gcfg)
• topological_sort(Gcfg)
• foreach vertex v ? Vcfg
• foreach ??-node?? ? v
• s ? ??.sources
• d ? def_use_chain(?.dest)
• IDF ? iterated_dominance_fronter(s)
• PossiblePlacements ?
  findPlacementOptions(IDF)
• place(?) ?
  selectBest(PossiblePlacements)
• distribute/duplicate ? to place(?)?

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Algorithm in Action

• FAST function from MediaBench testsuite

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Algorithm in Action
i
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Full Floorplanning Results

• Simple iterative approach

Spectacularly negative results

• Initial optimization minimizes data communication
• Full SA based floorplanning
• Reoptimization based to minimize floorplanning
• Full SA based floorplanning

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Incremental Floorplanning

• Incremental Placement Coudert et al
• Given an optimized placement and a set of changes
  to the netlist (e.g., due to technology
  remapping) modify the placement to improve it.
• Equally applicable to floorplanning

Initial Floorplan
Modified Floorplan
Perturbations
6
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Our Incremental Floorplanner
Initial Floorplan
Modified Floorplan
Perturbations
6
Incremental Floorplan

32/36 -
Incremental Floorplanner
27/30.4 -
-
1
5/5.6 -
4
16/18 -
-
11/12.4 -
3
2
2/2.3 -
9/10.1 -
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Our Incremental Floorplanner

• Calculate area room of each node bottom up
  slicing tree traversal
• Area redistribution
• Top down traversal
• Increase area if necessary
• Not enough space at root
• Aspect ratios become too distorted

Simple, yet effective Other more complicated
algorithms might work better
Modified Floorplan
Incremental Floorplan

32/36 -
27/30.4 -
-
1
5/5.6 -
4
16/18 -
-
11/12.4 -
3
2
2/2.3 -
9/10.1 -
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MediaBench Functions
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Incremental Floorplanning Results
Optimal Approach 12 Overall Wirelength
Reduction 25 Phi-node Wirelength Reduction
Normalized Wirelength
Our Approach 6 Overall Wirelength Reduction 8
Phi-node Wirelength Reduction
Benchmarks
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Related Work

• Hardware compilation projects using SSA
• PDGSSA form UCSB
• CASH CMU
• SA-C UCR
• Sea Cucumber BYU
• Physically aware behavioral synthesis techniques
• SA for scheduling, binding and floorplanning
  Prabhakaran97
• SA for binding and floorplanning Yung-Ming94
• Scheduling, allocation and binding Dougherty00
• Fasolt bus topology Knapp92
• High level synthesis Tarafdar00
• Incremental CAD
• Problem overview/challenges Coudert00
• Floorplanning Crenshaw99

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Conclusions

• Its been a long strange trip
• SSA a nice IR for hardware compilation
• Explicitly shows data flow
• Useful for exploiting parallelism
• Compiler techniques applied to hardware design
  can reduce wirelength
• They must be aware of physical information
• They must use an incremental floorplanning