Title: MultiGigabit SerialLink Integrated Silicon Transceiver
1Multi-Gigabit Serial-Link Integrated Silicon
Transceiver
- M.Sc. Thesis
- By
- Mohyee Mikhemar
- Under supervision of
- Prof. Hani Fikry
- Dr. Khaled Sharaf
2Outline
- Introduction to Optical Communications
- Thesis objective and flow
- TIA design
- CDR system design
- CDR circuit design
- Conclusion and Future Work
3Modern Optical Transmitter
4Optical Fiber Link
5Modern Optical Receiver
6Thesis Objective
- Design of integrated circuits and systems for
optical communication transceivers on silicon.
Transceiver blocks
Laser Driver
High voltage swing prohibit Silicon implementation
Low noise, high gain, broadband amplifier
TIA
- Design include
- System Level design
- Circuit Level design
A CDR will be designed on System and Circuit
levels
PLL-CDR
Future Work
7Target Standard
- SONET OC-192 line termination receiver for
short-haul links.
Synchronous Optical Network (SONET) SONET defines
optical carrier (OC) levels and electrically
equivalent synchronous transport signals (STSs)
for the fiber-opticbased transmission hierarchy.
- Short-haul links
- Transmission distance less than 40 Km
- No optical amplifiers are used to minimize the
cost - Receiver sensitivity limits the transmission
distance
8Design Flow
Link specs of different blocks to receiver
sensitivity
Link specs of different blocks to receiver
sensitivity
Design TIA for target Rx
Design CDR circuits
9Receiver Sensitivity
Sensitivity Minimum received power for a certain
BER
10Design Flow
Link specs of different blocks to receiver
sensitivity
Analyze common TIA topologies
Compare the analyzed topologies
Design TIA for target Rx
Design CDR circuits
11Common TIA Topologies (CB)
- The photodiode capacitance is large (0.1-0.5)pF
and does not scale with the technology. - The noise is mainly contributed by Q2, Rc.
- Challenges
- Severe trade-off on Rc.
- Rc ?, Gain ? , Noise ? .
- Rc ?, BW ?, Headroom ?.
- Headroom ?, Cj ?.
- Modern low voltage technologies suffer from
headroom problems
12Common TIA Topologies (CB w/ FB)
- The FB loop of CB must include inverting
amplifier. - Buffers drive the load capacitance.
- The complexity of the circuit affects its noise
and power performance.
13Common TIA Topologies (CE w/ FB)
- CE can not be used in open loop configuration
because - The high input impedance will draw less current
from the photo-detector. - The high gain will narrow the bandwidth.
- FB is deployed to decrease the input impedance.
- The load capacitance limits the bandwidth
14Common TIA Topologies (CE w/ buff FB)
- A CC buffer is added to isolate the main
amplifier from the load capacitance.
A. Buchwald and K. Marin, Integrated
Fiber-Optic Receivers , Kluwer, 1995.
15Design Flow
Link specs of different blocks to receiver
sensitivity
Analyze common TIA topologies
Compare the analyzed topologies
Design TIA for target Rx
Design CDR circuits
16Figure of Merit
0.5 SiGe Process with fT60 GHz and 3.3 V supply
voltage
M. Mikhemar, K. Sharaf and H. Ragai, On the
Performance of Transimpedance Amplifier,
proceedings of the Midwest Symposium, Cairo,
Egypt. December 2003.
17Design Flow
Link specs of different blocks to receiver
sensitivity
Analyze common TIA topologies
Compare the analyzed topologies
Design TIA for target Rx
Design CDR circuits
18TIA for OC-192
- AMS 0.35 SiGe technology with 3.3 V supply and
fT60 GHz
19Topology Analysis
20Peaking Control
The second order system is designed to control
the peaking
21Simulation Results
22Comparison with publications
Based on only schematic level simulation
FoM10.log(1000.FoM) RCG Regulated Common
Gate 0.1 HEMT 0.1InGaAs/AlGaAs
23Design Flow
Link specs of different blocks to receiver
sensitivity
Analyze common TIA topologies
Choose CDR architecture
Compare the analyzed topologies
Design CDR loops for target Rx
Design TIA for target Rx
Verify design using simulations
Design CDR circuits
24CDR
- CDR must provide two important functions
- Clock Recovery
- Data Regeneration
- Target CDR must
- Satisfy SONET jitter requirements
- Achieve stable operation
- Accommodate process variation
25Architecture of Choice
26Phase Detector of Choice
- If A B ? C, clock is early.
- If A ? B C, clock is late.
- If A B C, no transition.
27Design Flow
Link specs of different blocks to receiver
sensitivity
Analyze common TIA topologies
Choose CDR architecture
Compare the analyzed topologies
Design CDR loops for target Rx
Design TIA for target Rx
Verify design using simulations
Design CDR circuits
28Linear Model of the dual loop
29Dual Loop Analysis
- Third order, type II loop
- The system produces 3 poles and a zero
- The locations of the 3 poles and the zero are
adjusted using Sz, Sp, K, N. - The target of the analysis is to express the
closed loop poles in terms of loop parameters
30Proposed Dual loop Analysis
Complex domain
31Dual Loop stability Design
32Design Equations
To Satisfy Jitter tolerance
To Suppress the unwanted activity on the control
line
Substituting in the developed model
33Linear System Simulation Results
- Jitter tolerance performance
- Stability performance
- Proposed model verification
34Design Flow
Link specs of different blocks to receiver
sensitivity
Analyze common TIA topologies
Choose CDR architecture
Compare the analyzed topologies
Design CDR loops for target Rx
Design TIA for target Rx
Verify design using simulations
Design CDR circuits
35Simulink System Simulation
- Complete library of all CDR components was built
using simulink.
36Simulation Results
FLL Active
PLL Active
- a) Mux Control signal b) VCO control voltage
37Simulation Results (FLL acquisition)
During Acquisition
After Locking
38Simulation Results (PLL acquistion)
During Acquisition
After Locking
39Jitter Tolerance
Jitter Intolerant CDR
Jitter tolerant CDR
40Jitter Tolerance Measurements
41Design Flow
Link specs of different blocks to receiver
sensitivity
Analyze common TIA topologies
Choose CDR architecture
Compare the analyzed topologies
Design CDR loops for target Rx
Design TIA for target Rx
Verify design using simulations
Design CDR circuits
42CDR circuit design
Low speed
High speed
Done
Done
Done
43Alexander Phase Detector
44Alexander Phase Detector (Cont.)
Differential Current Mode Logic
D-Flip Flop
XOR-gate
45Complete PD simulation
Late Clock
Early Clock
46CDR circuit design
Low speed
High speed
Done
Done
Done
Done
Done
47Charge pump design
48Upper current source
49Lower current source
50Common Mode Sensing Network
51Charge Pump Simulation
- Differential output current
52CDR circuit design
Low speed
High speed
Done
Done
Done
Done
Done
Done
53Loop Filter design
- Given
- K
- ?z
- ?p from system design and,
- VCO gain
- Charge pump current from circuit design
- The loop parameters are
54CDR circuit design
Low speed
High speed
Done
Done
Done
Done
Done
Done
Done
5510 GHz VCO
- A fully differential interpolating two stage
ring-based VCO is used
56Delay Cell
57VCO Simulation Results
- Wide tunning range 6 GHz
- Phase noise -72.64 dBc _at_ 1 MHz offset
58CDR circuit design
Low speed
High speed
Done
Done
Done
Done
Done
Done
Done
Done
59Design Flow
Link specs of different blocks to receiver
sensitivity
Analyze common TIA topologies
Choose CDR architecture
Compare the analyzed topologies
Design CDR loops for target Rx
Design TIA for target Rx
Verify design using simulations
Design CDR circuits
60Conclusion
- Different TIA topologies have been thoroughly
studied and a proposed FoM has been reported. - A differential CE with double buffered TIA
circuit has been designed using 0.35 ?m SiGe
technology for OC-192 featuring a FoM of 28.3. - A linear model based procedure has been
formulated to speed up the design cycle of the
CDR.
61Conclusion (Cont.)
- A dual loop CDR for OC-192 has been designed and
simulated on behavioral level using the
formulated procedure. - A jitter tolerance testbench has been developed
to validate OC-192 jitter tolerance standard
mask. - The circuits of the different building blocks for
the dual loop CDR have been designed and
simulated based on differential CML technique
using 0.35 ?m SiGe technology .
62Future Work
- Fabricate the complete chip using AMS 0.35 ?m
SiGe technology. - Integrate the digital framer on the same chip.
- Study the capabilities of deep submicron CMOS
technologies for 10/40 Gbit/s operation.