Digital IC Layout Techniques

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Digital IC Layout Techniques
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Standard Cells
N Well
Cell height 12 metal tracks Metal track is
approx. 3? 3? Pitch repetitive distance
between objects Cell height is 12 pitch
Out
In
2?
Rails 10?
GND
Cell boundary
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Standard Cells
With silicided diffusion
With minimaldiffusionrouting
Out
In
Out
In
GND
GND
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Standard Cells
2-input NAND gate
A
B
Out
GND
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Standard Cell Layout Methodology 1990s
Mirrored Cell
No Routing channels
VDD
VDD
M2
M3
GND
GND
Mirrored Cell
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Two NMOS in Series
Out
A
B
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Two NMOS in Parallel
Out
A
B
Out
B
A
GND
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PDN of a Complex Gate-1
Out
A
C
B
Out
A
C
B
GND
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PDN of a Complex Gate-2
C
B
Out
A
Out
C
A
B
GND
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Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
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Stick Diagrams
Contains no dimensions Represents relative
positions of transistors
Inverter
NAND2
Out
Out
In
A
B
GND
GND
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Stick Diagrams
Logic Graph
A
C
j
B
X C (A B)
C
i
A
B
A
B
C
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Two Versions of C (A B)
C
A
B
A
B
C
VDD
VDD
X
X
GND
GND
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Consistent Euler Path
X
C
VDD
i
X
A
B
j
A
B
C
GND
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OAI22 Logic Graph
X
PUN
A
C
C
D
B
D
VDD
X
X (AB)(CD)
C
D
A
B
A
B
PDN
A
GND
B
C
D
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Example x abcd
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Parasitic Capacitance

• Mainly three types of parasitic capacitances
  exist associated with a design/layout
• Diffusion capacitance
• Gate/poly capacitance
• Interconnect/wire capacitance

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Parasitic Resistance

• Mainly two types of parasitic resistances exist
  associated with a design/layout
• Interconnect resistance and
• Contact or Via resistance

• Interconnect resistance is calculated from Sheet
  
• Resistance and its length and width.

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contd
(2) Contact or Via resistance

• Possible Interconnect square/sheet resistance
  values
• Metal 0.2-0.8
• Contacts/vias 5-100