P326 Gigatracker Pixel Detector

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P326 Gigatracker Pixel Detector

• Requirements
• material budget, time resolution, radiation
  hardness,...
• Hybrid pixels sensor, readout chip, bump bonding
• Electronics system
• (Mechanics and) Cooling
• Resources - Workplan
• Possible interest in RD for CLIC

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P326 Proposal

• 10-11 branching ratio
• high intensity K beam
• high background rejection
• 5.1012 K decays/year
• 100 events by 2011

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P326 Beam
Tracking, momentum, time stamp

• modified NA48 K12 beam line
• 3.1012 protons on target (400GeV) gt 60 pions,
  20 protons, 14 electrons, 6 kaons
• overall particle rate 0.8GHz gt
  Gigatracker
• beam cross-section 12cm2 at GTK

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GTK Si Pixels
P. Riedler
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Required Gigatracker time resolution

• P(gt1hit in Dt) 1-exp(-Dtrate)

Dt ( 2s) _at_0.8GHZ _at_1GHZ 400
27 33 500 33
39 600 38 45
K ?pp0
Dependence of the signal to background (from K
?pp0 ) as a function of the gigatracker time
resolution
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Material Budget Requirements

• Full GEANT simulation
• Impact of GTK material budget
• beam momentum resolution
• angular beam resolution
• vertex resolution
• missing mass
• No significant degradation at 0.5Xo per plane

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Radiation Levels in Gigatracker (GTK)

• Calculated fluence 2. 1014 (1 MeV neq
  cm-2) 100 days
• For comparison
• ATLAS SCT/CMS TK 1.5 1014 (1 MeV neq cm-2) 10
  years
• Safety factors in estimates

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GTK Hybrid Pixel Design Parameters (Preliminary)
hybrid pixels

• Pixel cell size 300mm x 300mm
• Sensor thickness 200mm
• charge collection time vs signal amplitude
• Pixel chip thickness 100mm
• Bump bonding Pb-Sn
• Material budget 0.4 X0 (each station)
• Operating temp. T 5 C (in vacuum)
• Cooling 120mm CF radiator/support with
  peripheral cooling

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Si Sensors

• Radiation effects
• type inversion (higher Vb required)
• leakage current increase
• DIvola fne (a 5 x 10-17 A/cm)
• Remedies
• M-CZ material (to be studied)
• operation at low(er) temp (in vacuum...)
• I ? exp(-Eg/2kT)
• (up to 200mA/cm2 _at_ 25 C )
• DI reduction 16x _at_ 0 C
• periodic replacement of station

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GTK Pixel ASIC

• Technology CMOS8 (0.13mm)
• speed, density, power, (radiation hardness)
• availability/obsolescence, MPW access
• cost (prototyping, engineering run)
• frame contract at CERN for applications within
  the HEP community
• Conceptual study well advanced
• definition of system architecture
• noise (mixed-signal application)
• upcoming MPW submission of functional blocks
  (amplifier, discriminator, TDC, ...)

ALICE pixel ASIC (CMOS6 0.25mm) 8,192 pixel
cells
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Bump Bonding

• Bump bonding of 150mm pixel chips to 200mm
  sensors in volume production (ALICE SPD 107
  pixels)
• Pb-Sn (VTT/Finland)
• Thinning of pixel wafers (D200mm) is done after
  bump deposition
• Thinning/bb to 100mm (or less) requires
  prototyping
• Preliminary test under way with ALICE pixel dummy
  wafers
• Key issue flatness of sensors

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Readout Wafer Thinning
200mm Si wafer thinned to 150 mm
J. Salmi/VTT BOND03 CERN
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Chip Size - Power Management

• Power dissipation up to 2W/cm2 (preliminary
  estimate)
• Material budget constraints on coverage of beam
  area
• Lowest material budget with only pixel matrix in
  beam
• I/O pads and cooling at periphery
• This leads to power management problems
• Beam cross section adjusted ( rectangular) to
  ease matching of optimized chip layout
• without degradation of beam quality

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Configuration I
Pads for power supplies and clock (additional
material budget)
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Configuration II
Max rate on one chip, but chip smaller
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Configuration IV
60 mm
6 mm
12 mm
24 mm
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Time Stamp

• Fast discriminator with time walk compensation is
  key element
• TDC bin size 100ps
• TDC options
• one TDC per pixel cell (linear discharge)
• cell area, power dissipation, dead time
• group multiplexed TDC
• efficiency loss (must be limited to lt2)

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Chip size/data rate

• With a beam of 24 x 60 mm -gt 2 x 5 chips
• Assume chip matrix of 40 rows x 40 columns 12
  mm x 12 mm 144 mm2
• Pixel size 300 um x 300 um
• gt 40 x 40 pixels 1600 pixels
• Avg Rate of center column 96 MHz/cm2
• gt 86 kHz/pixel
• gt 138 MHz/chip
• gt 138 MHz/chip 32 bit 4.4 Gbit/s

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Cooling

• Power dissipation (pixel plane) 20W
• Operating temperature lt 5 C (gt sensor leakage
  current)
• CF radiator fins coupled to cooling circuit
• Adhesive/filler ( 50mm) thermal conductivity 1
  W/(m K)
• Cooling system options
• fluid coolant
• evaporative cooling
• C4F10
• C4F8
• Peltier cell ?

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Carbon Fibre (CF) Composites

• CTE (ppm/K) -1.5/12
• Th. conductivity (W/m K) 150 (M55J)
• 1,000 (K-1,100)
• 390 (Cu)
• 145 (Si _at_ T300K)
• Density (g/cm3 ) 1.9/2.2
• X0 (g/cm2) 42 ( 21 cm)
• ( 9.36cm for Si)
• 2-ply radiator thickness 120 mm

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Initial Situation

• Case A without cooling plane
• Case B with cooling plane and with different
  thermal contact resistances between the solids
• Total Heat Load of 2 W/cm²

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Results with ideal contact between materials
Case A B1 B2 B3 B4
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Temperature gradient of the Silicon Pixel
detector in dependence of the thermal
conductivity of the cooling plane
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Results with thermal resistance between materials
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Influence of the thermal resistance

• It is quite difficult to calculate the real
  thermal resistance of the contact surfaces
  between the materials.
• Differences between hand calculation and
  CFD-Simulation, show the influence of the bumps.

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Detector Development Team(Very preliminary)

• Sensors CERN 1 Phys Staff, 1 Fellow INFN
  Ferrara 1 PostDoc (tbc)
• Analog electronics CERN 1 Eng, 1 Fellow
  (but...) INFN Torino 2 Eng
• Electronic system integration CERN 1
  Eng INFN Ferrara (tbd) INFN Torino (tbd)
• CERN staff (sensors and system) for the time
  being fully committed to LHC activities (ALICE
  SPD)
• gt 2 FELL/DOCT student required (1 already
  available)
• Mechanics cooling CERN), Ferrara

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Planning (Preliminary)

• System architecture def. simulation H1 YR1
• Small scale prototype submission Q3 YR1
• Engineering run 1 submission Q2 YR2
• Engineering run 2 submission Q2 YR3
• Production of final chip Q1 YR4
• Detector assembly Q3 YR4
• YR1 start of PH support funding