Title: Constructing Stronger Registers from Weaker Ones
1Constructing Stronger Registers from Weaker Ones
Yuliang Bao Adesola
Omotayo Instructor Dr. Lisa Higham
December 11, 2003
2 Outline
- Definitions
- Views of a system
- Registers
- Constructions
- Conclusions
3Definition Atomic operation
- Execution performed as an indivisible action
- Example Transfer money from a bank account to
another - Get the balance of source account
- Subtract the amount to transfer
- Write the new balance of source account
- Get the balance of destination account
- Add the amount to transfer
- Write the new balance of destination account
4Definition Operation Execution
- A specific instance of executing an operation
- Example Transfer 20 from account 1 to account
2 - Get the balance of account 1
- Subtract the amount to transfer
- Write the new balance of account 1
- Get the balance of account 2
- Add the amount to transfer
- Write the new balance of account 2
5Definition Serializable Execution Order
- Scheduling of events so that the net effect is
the same as if the events had been executed in
some serial order - Example Transfer 20 from account 1 to account
2 - Get the balance of account 1
- Get the balance of account 2
- Subtract the amount to transfer from account 1
- Add the amount to transfer to account 2
- Write the new balance of account 1
- Write the new balance of account 2
Operation A
Operation B
Operation C
6Definition Precedence Relations
- Precedence Relations
- Precede A B ?a ? µ(A) ?b ?
µ(B) a b - Can affect A B ?a ? µ(A) ?b ?
µ(B) a b - Example Transfer 20 from account 1 to account
2
Operation A
Operation B
a1 Get the balance of account 1 a2 Get the
balance of account 2
b1 Subtract transfer amount from 1 b2 Add the
amount to transfer to 2
7Definition System Execution
- A set of operation executions plus temporal
precedence relations on those operations - A triple ltS, , gt where S is a finite
or countably infinite set whose elements are
called operation executions, and and
are precedence relations on S
8Axioms
- A1 The relation is an irreflexive
partial ordering - A2 If A B then A B and B
A - A3 If A B C or A B
C then A C - A4 If A B C D then A
D - A5 For any A, the set of all B such that A
B is finite
Time
A B C D
9Views of a system
- Lower Level
- A system execution implementing a higher level
system execution e.g ltS, , gt - High Level
- A set of lower level operations that implement it
e.g ltH, , gt - Let E, , µ be a model for ltS, ,
gt, and let the mapping of µ on H be µ(H)
Uµ(A) A ? H then - G H ?g ? µ(G) ?h ? µ(H) g
h - G H ?g ? µ(G) ?h ? µ(H) g
h or g h
10Views of a system
- Higher Level
- A system execution ltS, , gt
implementing a system execution ltH, ,
gt - H1 Each element of H is a finite, nonempty set
of elements of S - H2 Each element of S belongs to a finite,
nonzero number of elements of H - H3 For any G, H ? H if G H then G
H
11Registers Space
- Usually specified in the following format x,y,z
12Registers Access
- x Coordinate
- Single-Writer Single-Reader (SWSR)
- Multi-Writer Single-Reader (MWSR)
- Single-Writer Multi-Reader (SWMR)
- Multi-Writer Multi-Reader (MWMR)
13Registers Values
- y Coordinate
- Boolean 0, 1
- Multi-valued 1n
14Registers Strength
- z Coordinate
- Safe
- Regular
- Atomic
15RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
16RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
17Construction 1SRSW,MV,S/R ? MRSW,MV,S/R
- Let ?1,,?m be single-reader, n-valued registers,
where each ?i can be written by the same writer
and read by process i, and construct a single
n-valued register ? in which the operation ? µ
is performed as follows - for all i in 1,,m do ?i µ od
- and process i reads ? by reading the value of
?i. If the ?i are safe or regular registers, then
? is a safe or regular register, respectively
18SRSW,MV,S/R ? MRSW,MV,S/R
19RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
20Construction 2MRSW,B,S ? MRSW,MV,S
- Let ?1,,?n be boolean m-reader registers, each
written by the same writer and read by the same
set of readers. Let ? be the 2n-valued, m-reader
register in which the number with binary
representation µ1 µn is written by - for all i in 1,,n do ?i µi od
- and in which the value is read by reading all
the ?i. If each ?i is safe, then ? is safe
21MRSW,B,S ? MRSW,MV,S
22RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
23Construction 3MRSW,B,S ? MRSW,B,R
- Let ? be an m-reader boolean register, and let x
be a variable internal to the writer (not a
shared register) initially equal to the initial
value of ?. Define ? to be the m-reader boolean
register in which the write operation ? µ
is performed as follows - If x ? µ then ? µ
- x µ fi
- and a read of ? is performed by reading ?. If ?
is a safe then ? is regular register
24MRSW,B,S ? MRSW,B,R
25RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
26Construction 4(MRSW,B,R ? MRSW,MV,R)
Algorithm
- The write ? ? is performed by
- 1 ?? 1
- 2 for i ? -1 step 1 until 1 do ?i 0 od
- A read is performed by
- 1 ? 1
- 2 while ?? 0 do ? ? 1 od
- 3 return ?
- Notation
- ?1,, ?n MRSW,B,R
- ? MRSW,MV,R
27Construction 4(MRSW,B,R ? MRSW,MV,R)
?1 ?2 ??-1 ?? ?n
0 0 0 1
1
28RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
29Construction 5(SRSW,MV,R ? SRSW,MV,A)
- Notation
- w, r write and read processes
- V a finite set
- v SRSW,MV,R written by w and read by r and w
- V ? V ? 1,2,3 ? true, false
- num(v) initially 3
- E.g. for v (x,y,i,k), old(v) x, new(v) y,
num(v) i, col(v) k - c SRSW,B,R written by r and read by w
- V SRSW,MV,A written by w and read by r
- nc, x, rv, rv, nuret local variables
- nuret initially, false nuret true if the
reader returned the y value on the preceding
read.
30Construction 5(SRSW,MV,R ? SRSW,MV,A)
Algorithm
- The write v y is performed by
- 1 nc ?c
- 2 x old(v)
- 3 for i 1 until 3 do v (x,y,i,nc) od
31Construction 5(SRSW,MV,R ? SRSW,MV,A)
- A read is performed by
- 1 rv rv
- 2 rv v
- 3 c col(rv)
- 4 if num(rv) 3
- 5 then nuret true
- 6 return new(rv)
- 7 else if nuret ? col(rv) col(rv) ?
num(rv) ? num(rv) 1 - 8 then return new(rv)
- 9 else nuret false
- 10 return old(rv)
- fi
- fi
32Construction 5(SRSW,MV,R ? SRSW,MV,A)
rv
Case 2
(x, y, 2, k)
ret x
33Construction 5(SRSW,MV,R ? SRSW,MV,A)
Case 2
nuret F
34Construction 5(SRSW,MV,R ? SRSW,MV,A)
rv
(x, y, 3, k)
Case 3
ret y
col(rv) col(rv) k, 2 ? 3-1
rv
rv'
(y, z, 1, k)
(y, z, 2, k)
ret z
col(rv) col(rv) k, 1 ? 2-1
35RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
36Construction 6(SRSW,B,A ? SRSW,MV,A)
Algorithm
when write(R,v) occurs // the writer writes
the value v to R 1 Bv 1 2 for i
v 1 downto 0 do Bi 0 3 ack(R)
Notation B0,Bk-1 SRSW,B,A initially all
0, except Bi 1 (i initial value
of the simulated register R)
37Construction 6(SRSW,B,A ? SRSW,MV,A)
Algorithm
when read(R) occurs // the reader reads
from R 1 i 0 2 while Bi 0 do i i
1 // forward scan 3 up, v i 4
for i up 1 downto 0 do // backward scan 5
if Bi 1 then v i 6 return (R,v)
38Proof of algorithm(SRSW,B,A ? SRSW,MV,A)
- No overlap between read and write Every read
returns the value of the latest preceding write. - Overlap between reads R1, R2 and write w2(avoid
new-old value problem)
0 1 5 8 k-1
0 0 1 1 0
B
0 1 5 8 k-1
0 0 1 1 0
B
R
R
R1
R1
R2
R2
r1(R) r2(R)8
39RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
40Construction 7 (SRSW,MV,A ? MRSW,MV,A)
- One writer pw and n readers p1, , pn
- Vali (value, seq) written by pw and read by
reader pi, 1 ? i ? n - Reporti,j The value returned by the most
recent read operation performed by pi written by
pi, read by pj, 1 ? i,j ? n - Initially, Reporti,j Vali (v0,0), 1 ? i,j
? n, v0 initial value of R
Algorithm
when write(R,v) occurs // the writer writes v
to R 1 seq seq 1 2 for i 1 to n
do Vali (v, seq) 3 ack(R)
41Construction 6(SRSW,B,A ? SRSW,MV,A)
i 1 2 3 4 5 6
1 1 1 1 1 1
5 5 5 5 5 5
V
Vali
seq
Write(R,10)
10 10 10 10 10 10
6 6 6 6 6 6
V
Vali
seq
42Construction 7 (SRSW,MV,A ? MRSW,MV,A)
Algorithm
- when readr(R) occurs // the reader
pr reads from R - 1 (v0, s0) Valr // value
reported to pr by writer - 2 for i 1 to n do
- (vi, si) Reporti,r // value
reported to pr by reader pi - 3 let j be such that sj maxs0,s1,,sn
- 4 for i 1 to n do
- Reportr,i (vj, sj) // pr
reports to each pi - 5 returnr (R,vj)
43Proof of algorithm (SRSW,MV,A ? MRSW,MV,A)
- P4 read Val4 where s0 3,
- P4 receives Report(i,4), ? i
read4(R)
Seq in Report(i,j)
1 2 3 4 5 6
1 6 6 6 6 6 6
2 8 8 8 8 8 8
3 3 3 3 3 3 3
4 2 2 2 2 2 2
5 4 4 4 4 4 4
6 1 1 1 1 1 1
(2) s2 maxs0,,s6
max3,6,8,3,2,4,1 8
44Proof of algorithm (SRSW,MV,A ? MRSW,MV,A)
(1) P4 receives Report(i,4), ? i
Seq in Report(i,j)
1 2 3 4 5 6
1 6 6 6 6 6 6
2 8 8 8 8 8 8
3 3 3 3 3 3 3
4 8 8 8 8 8 8
5 4 4 4 4 4 4
6 1 1 1 1 1 1
(2) Assume s0 3 s2 maxs0,,sn
max3,6,8,3,2,4,1 8
45Proof of algorithm (SRSW,MV,A ? MRSW,MV,A)
- To prove For any admissible execution ?, ? a
permutation ? of the high-level operations in ?,
such that ? preserves the order of
non-overlapping operations, and every read
operation returns the value of the latest
preceding write. - Constructing ? in two steps
- (1) Put in ? all the write operations
according to their order in ? - (2) add each read operation to ? according
to its response in ? - w(x,T) ? r(x,T) ? w(y,T1)
46Proof of algorithm (SRSW,MV,A ? MRSW,MV,A)
Lemma Let op1 and op2 be two high-level
operations in ? such that op1 ends before op2
begins. Then op1 precedes op2 in ?.
- Proof For a read operation, r, by pi that
returns a value with timestamp T, - A write w follows r in ? (by contradiction,
suppose w ? r in ?)
47Proof of algorithm (SRSW,MV,A ? MRSW,MV,A)
Proof For a read operation, r, by pi that
returns a value with timestamp T,
- A write w precedes r in ? (Vali written by
w or a later write)
- A read r by pj follows r in ? (Report(i)
written by pi during r or later)
48RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
O(n)
O(K)
O(K)
O(1)
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(1)
O(K)
SRSW,B,R
SRSW,MV,S
MRSW,B,S
SRSW,B,S
49Construction 8 (MRSW,MV,A ? MRMW,MV,A)
- m writers (p0,, pm-1) and n readers (p0,,
pn-1) - TSi The vector timestamp of writer pi,
- written by writer pi and read by
all writers - Vali (value, vector timestamp),
- written by writer pi and read by
all readers - Initially, TSi ?0,,0? and Vali initial
value of R, 0 ? i ? m 1
50Construction 8 (MRSW,MV,A ? MRMW,MV,A)
- // writer pw writes v to register R, 0 ? w ? m
1 - when writew(R,v) occurs
- 1 ts NewCTS()
- 2 Valw (v, ts)
- 3 ackw(R)
- procedure NewCTSw() // writer pw obtains a
new TS - 1 for i 0 to m-1 do // extract the i-th
entry - ltsi TSi.i // from TS of
i-th writer - 2 ltsw ltsw 1 // increment own
entry - 3 TSw lts // write to
shared register - 4 return lts
51Construction 8 (MRSW,MV,A ? MRMW,MV,A)
- // reader pr reads from register R, 0 ? r ? n 1
- when readr(R) occurs
- 1 for i 0 to m - 1 do
- (vi, ti) Vali // v and
t are local variables - 2 let j be such that tj
maxt0,t1,,tm-1 - //
lexicographic max - 3 returnr(R,vj)
52Proof of algorithm (SRSW,MV,A ? MRSW,MV,A)
Write2 (R, 10)
0 1 2
0 3 2 1
1 2 2 1
2 2 1 1
0 1 2
0 3 2 1
1 2 2 1
2 3 2 2
TS
TS
Val2 (10, TS2)
Readr (R)
0 1 2
0 3 2 1
1 2 2 1
2 3 2 2
TS
TS2 maxTS0, TS1, TS2 Return v2
53Proof of algorithm (MRSW,MV,A ? MRMW,MV,A)
- Lemma The lexicographic order of the timestamps
is a total order consistent with the partial
order in which they are generated.
TS
0 1
0 0 0
1 0 0
0 1
0 1 0
1 0 0
0 1
0 1 0
1 1 1
0 1
0 2 1
1 1 1
write0(R)
write1(R)
write0(R)
TS0 ? TS1
54Proof of algorithm (MRSW,MV,A ? MRMW,MV,A)
- ? an admissible execution
- ? a permutation of the high-level operations in
? (same as - the previous algorithm)
- Constructing ? in two steps
- (1) Put in ? all the write operations
according to their lexicographic ordering on the
timestamps in ? - (2) add each read operation to ? according
to its response in ? - w(x,VT) ? r(x,VT) ? w(y,VT)
55Proof of algorithm (MRSW,MV,A ? MRMW,MV,A)
Lemma Let op1 and op2 be two high-level
operations in ? such that op1 ends before op2
begins. Then op1 precedes op2 in ?.
- Proof For a read operation, r, by pi that
returns a value with timestamp VT, - A write w follows r in ? (by contradiction,
suppose w ? r in ?)
56Proof of algorithm (MRSW,MV,A ? MRMW,MV,A)
Proof For a read operation, r, by pi that
returns a value with timestamp VT,
- A write w by pj precedes r in ? (Val j
written by w or a later write)
- A read r by pj follows r in ? (TS
non-decreasing lexicographic order)
TS(r) ? TS(r)
57RegistersHasse Diagram
m of writers n of readers k of values
MRMW,MV,A
O(m)
MRSW,MV,A
MRMW,MV,R
O(n)
MRSW,MV,R
MRSW,MV,R
SRSW,MV,A
5
O(n)
O(K)
O(K)
O(1)
4
SRSW,B,A
MRSW,MV,S
SRSW,MV,R
MRSW,B,R
MRSW,MV,S
O(n)
O(K)
5
O(1)
O(K)
1
4
O(1)
3
2
SRSW,B,R
SRSW,MV,S
MRSW,B,S
1
3
O(K)
2
O(n)
O(1)
SRSW,B,S
58Conclusions
- Lamports paper and other related papers were
thoroughly reviewed. - Eight Constructions and their proofs are well
understood and described in this project. - Five new constructions were found and presented
by studying previous constructions.
59Thank you!
- Dr. Lisa Higham
- Fellow graduate students
60References
- L. Lamport, On Interprocess Communication,
Parts 1 and 2, Dec. 25, 1985 - H. Attiya and J. Welch, Distributed Computing