ECE 747 Digital Signal Processing Architecture SoC Lecture

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ECE 747 Digital Signal Processing
ArchitectureSoC Lecture Working with DRAM
April 3, 2007 W. Rhett Davis NC State University
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Todays Lecture

• DRAM Introduction
• DRAM Latencies

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Introduction

• Perhaps more than any other single factor, DRAM
  heavily influences SoC Architecture
• Our goal is to accurately predict the average
  throughput of our architecture.
• Questions we need to answer For a given
  architecture, how do we
• choose the right data-width for the DRAM?
• choose the right clock-frequency for the DRAM?
• configure the Dynamic Memory Controller for the
  correct latencies?

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Types of DRAM

• SDRAM (Synchronous DRAM) Synchronized to bus
  clock frequency, Achieves higher
  clock-frequencies than normal DRAM because it is
  designed to work at a specific frequency
• DDR SDRAM (Double Data Rate SDRAM) Achieves
  higher throughput by reading/writing data on both
  clock transitions (rising and falling)
• Why is this necessary? Cant we just use more
  chips?
• DDR2 SDRAM Allows bus clock to be 2X internal
  clock of DRAM, achieves higher clock-frequencies
• Each of these improvements comes with added
  latency

• Because adding a pin to the SoC is one of the
  most costly design decisions, consumes lots of
  area and adds lots of wire delay

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Array-Structured Memory Architecture
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Source Rabaey, et al, Digital Integrated Circuits
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Hierarchical Memory Architecture
Most DRAMs are organized in multiple blocks or
banks
Source Rabaey, et al, Digital Integrated Circuits
Advantages
1. Shorter wires within blocks
2. Block address activates only 1 block gt power
savings
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SDRAM Pins

• Address pins are in two groups
• Column/Row Address pins (each address provided on
  a different cycle)
• Bank Address
• Example 256Mb (32Mx16 4banks)
• 13 column/row address pins (green)
• 2 bank address pins (white)
• 16 data pins (blue)

Source Micron 256Mb DDR2 SDRAM Datasheet
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Todays Lecture

• DRAM Introduction
• DRAM Latencies

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Types of Latencies

• Read/Write Latencies
• CAS/CL
• DQSS
• Command Latencies
• RCD
• RP
• RAS
• RC
• RRD
• WTR
• WR

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CAS Latency (CAS/CL)

• Colmn Address Strobe/Select Latency Delay
  between read command and arrival of data
• Source Micron 256Mb SDRAM Datasheet

CAS 3
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Moving Between Columns/Banks

• Reads within the same column and between banks
  incur no additional latency
• Configured for bursts of 4, reads to separate
  column addresses in different banksSource
  Micron 256Mb SDRAM Datasheet

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Data Strobe Delay (DQSS)

• Time between issuing of write command and when
  first data-value is expected to be valid

Source Micron 256Mb DDR2 SDRAM Datasheet
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Command Latencies

• The previous latencies dont affect throughput,
  because they can be pipelined
• Command latencies, however, affect throughput,
  because they affect how long you must wait before
  issuing a new command
• Commands
• ACTIVE Activate (or open) a row for
  read/write
• PRECHARGE Precharge (or close a row)
• READ
• WRITE
• Only ONE ROW AT A TIME may be active in each bank
• A Row must be closed before another one can be
  opened

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Types of Latencies

• Read/Write Latencies
• CAS/CL Column Address Strobe/Select Latency
• DQSS Data Strobe Delay
• Command Latencies
• RCD Row-to-Column or Row Command Delay
  (ACTIVE to READ or WRITE)
• RP Row Precharge (PRECHARGE to ACTIVE)
• RAS Row Address Strobe/Select (ACTIVE to
  PRECHARGE)
• RC (ACTIVE to ACTIVE same bank)
• RRD Row to Row Delay (ACTIVE to ACTIVE
  different banks)
• WTR Write to Read Delay (WRITE to READ)
• WR Write Recovery (WRITE to PRECHARGE)

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Command Latencies Illustrated

• This figure illustrates which latency value to
  expect when one command follows another

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RCD, RP, RAS, RC Latencies
Source Micron 256Mb SDRAM Datasheet
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Comparison of Micron Memories
256 MbSDRAM 256 MbDDR SDRAM 256 MbDDR2 SDRAM
fclk (MHz) 167 200 333
CAS/CL (cyc.) 3 3 5
RCD (ns) 15 15 15
RP (ns) 15 15 15
RAS (ns) 37 40 40
RC (ns) 60 55 55
RRD (ns) 14 10 7.5
WTR (cyc.) 1 2 7.5
WR (ns) 14 15 15
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Comparison of Micron Memories
256 MbSDRAM 256 MbDDR SDRAM 256 MbDDR2 SDRAM
fclk (MHz) 167 200 333
CAS/CL (cyc.) 3 3 5
RCD (cyc.) 3 3 5
RP (cyc.) 3 3 5
RAS (cyc.) 7 8 14
RC (cyc.) 11 11 19
RRD (cyc.) 3 2 3
WTR (cyc.) 1 2 3
WR (cyc.) 3 3 5