CNTFETbased circuits In the presence of metallic tubs and variations

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CNTFET-based circuitsIn the presence of metallic
tubs and variations
Malgorzata Chrzanowska-Jeske Acknowledgments Bas
ed on work by PhD student Rehman Ashraf
Contributor Dr. Siva Narendra, Tyfone
Electrical and Computer Engineering
Department Maseeh College of Engineering and
Computer Science Portland State
University September 23, 2009
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Outline

• CNT and CNTFETs
• Challenges
• Design in the presence of metallic tubes
• Functional Yield
• Presence of variations
• Possible solutions to consider
• Summary

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Carbon Nanotubes

• Depending on the chirality a CNT can be either
  metallic or semiconducting

• Plasma CVD 11 metallic (semiconducting
  89?2.3)
• General CVD30 metallic
• HiPCo 39 metallic (semiconducting 61?7.6)
• Newest (Qu, Nano Letters 2008) Preferential
  Synthesis - 4
• Self sorting during deposition (Engel, ACS Nano,
  2008, LeMieu, Sciencex 2008)

N. Srivastava, et al, VMIC, 2004
Metallic Tubes affect functionality of logic gates
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Carbon Nanotube FETs

• Similar structure to CMOS
• Compatible to current design infrastructure
• CNT as the channel

• CNT-FET devices 6x faster than NMOS and 13x
  faster than PMOS (Deng et al. ISSCC, 2007)
• Better for VDD scaling potential for low power
• Ballistic transistors with high K dielectrics
  (Javey et al. Nano letters, 2005)

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CNTFETs vs. Si MOSFETs
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Challenges

• Process control
• Chirality
• semiconducting vs. metallic
• Contact Schottky barrier
• Alignment and diameter variation
• Spacing distribution
• Performance variability and power dissipation

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Tube Configurations

• Shared Tube
• (Javey et al. Nano letters,2004)

• Parallel Tube
• (Deng et al. ISSCC, 2007)

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Delay of Logic Gate
Ntu8
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Impact of Metallic Tubes
Metallic Tubes increase contention current from
OFF network Impacts both Delay Static Power
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Functional Yield (Yf)
Percentage of Logic gates that meet both Delay
and Leakage constraints

Total Gates (n)
Functional Yield (Yf) f n
Leakage Constraint
Delay Constraint
(f)
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Parallel Tube Inverters
Monte Carlo simulation, n10,000, Ntu16

Yf66.5
Yf100
Yf88.6
44.6
47.8
100
18.7
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Metallic Tubes Delay ?, Static Power ?, Yf ?
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In the presence of metallic tubes
Tube Stacking
Transistor Stacking
Expectations Contention Current ?
Static Power ? Functional Yield ?
Performance ?
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Functional Yield Analytical Model
For an allowed delay constraint the maximum
Number of metallic tubes that can be
tolerated
The functional yield Yf of an inverter is
therefore the sum of the probabilities of having
0 to Nmmax metallic tubes
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Functional Yield Comparison
INVERTER, n10,000

Transistor Stacking
Tube Stacking
Parallel Tube
Pm 5
Pm 10
Pm 15
Transistor Stacking Functional Yield ?
1.0X?3.1X Tube Stacking Functional Yield ?
1.0X?3.3X
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Configuration Comparison
n10,000, Ntu8, Pm10
Stacking Configurations Functional Yield up 2X
, Static Current up 7X , Delay up 4x
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MC vs. Analytical
Lines Analytical Model Symbol MC
simulation n10,000
Accurate Analytical Model Explicable Trends
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Metallic tube Removal
Current-Induced Electrical Burning Not easily
scalable for large VLSI systems Requires
contact with each individual nanotube Selective
Chemical Etching (SCE) Removes tubes based on
cutoff diameters of tubes Different cutoff
diameters for metallic(DCM) and semiconducting
(DCS) nanotubes
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Tube Removal by SCE
Diameter(dCNT) m1.5nm , 3s0.5nm
27 of CNTs dCNTlt1.4nm, 0.1 metallic tube
remains Total tubes removed 27 metallic tubes
with dCNTgt1.4nm
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Impact of SCE on Delay
Inverter with 4 tubes in pull-up(PU) and
pull-down(PD) network
No removed tubes
2 from PU 1 from PD
All from PU none from PD
Large variation in delay, worst case open circuit
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Impact of SCE on Delay
Pr0
Pr31
Pr34.7
No Selective Etching
Yf100
Yf3.3
Yf5.4
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Impact of SCE on Yield
Percentage of ? metallic tubes Percentage of ?
tubes removed (Pr) Functional yield ? of
gates(Yf)
Pm 5 Pr31
Pm 10 Pr34.7
Pm 15 Pr38
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Tube Level redunduncy
Minimum number of tubes to avoid open circuits
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Impact of TLR on Yield
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CNT Images
Single-walled Carbon nanotube
Carbon Nanotube Forest
BrewrScience.com
separationsnow.com
Carbon nanotube
nature.com
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Diameter Variation

• dCNT - ? 1.5nm, 3s 0.5nm

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Multi Tube Transistor

• Average density of CNTs obtained today is between
  10-50 CNTs/um
• 50 CNTs/um means CNT pitch of 20nm
• 10 CNTs/um means CNT pitch of 100nm
• To obtain better performance than CMOS 250
  CNTs/um are required
• 250 CNTs/um means CNT pitch of 4nm
• Significant charge screening problem

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8 Tube Transistor

• Perfect alignments
• diameter variation
• Fix Pitch 2.5nm,
• Pitch variation ? 2.5nm, 3s 0.5nm

Pm5
After SCE
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Summary

• Circuit design is difficult if metallic tube
  content is over 20 (General CVD, HiPCo)
• For metallic tube content of 10 (Plasma CVD)
• Architecture that utilizes delay, power and yield
  trade-off required.
• Shared Tube and Parallel tube (Delay is Critical)
• Transistor and Tube Stacking (Power and Yield
  are Critical)
• Design functional block proof-of-concept to
  demonstrate delay, power, yield trade-off
• Selective Chemical Etching - to remove Metallic
  Tubes
• Metallic tube removal - large variation in delay
  and functional yield of gates (worst - open
  circuit).
• Tube Level Redundancy increases the functional
  yield of logic gates
• Need to focus on circuits not gates for better
  averaging
• Improve selectivity of tube removal