III-V HBT device physics: what to include in future compact models

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III-V HBT device physics what to include
infuture compact models
Workshop on Compact Modeling for RF-Microwave
Applications, Oct.. 3, 2007, Boston, Mass.
Mark Rodwell University of California, Santa
Barbara
rodwell_at_ece.ucsb.edu 805-893-3244, 805-893-2362
fax
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Fast InP Transistors What Are They For ?
microwave op-amps high IP3 at low DC power at
2-10 GHz
microwave ADCs and DACsmore resolution more
bandwidth
Power amplifiers for V-band W-band
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Current IC Projects ? Modeling Challenges
340 GHz, 70 mW amplifiers (DARPA SWIFT)device
and IC layout parasiticsbreakdown safe
operating area, thermal stabilitytf and Ccb
over full signal swing
M. Jones (UCSB), J. Hacker (Teledyne)
200 GHz digital logicCcb vs (Ic , Vce)
---precise modelling of Kirk effect for low
C/IIC interconnect modelling
Z. Griffith
mm-wave op-amps? low IM3 _at_ 2 GHz Ccb vs Ic and
Vce----residual distortiongm vs Ic --- modeling
of gain, and of gm nolinearitiescompact, precise
modelling of interconnect parasitics---phase
margin !
M. Urteaga (Teledyne)
Z. Griffith
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Technology Status Roadmap
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512 nm InP DHBT Low-Volume Production
500 nm mesa HBT
150 GHz M/S latches
175 GHz amplifiers
LaboratoryTechnology
UCSB
UCSB / Teledyne / GCS
DDS IC 4500 HBTs
mm-wave op-amps
500 nm sidewall HBT
Production
( Teledyne )
Teledyne / BAE
Teledyne / UCSB
Teledyne
20 GHz clock
high OIP3 _at_ 2 GHzwith low power dissipation
f? 405 GHz fmax 392 GHz Vbr, ceo 4 V
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256 nm InP DHBTResearch? Development
150 nm thick collector
70 nm thick collector
200 GHz master-slavelatch design
60 nm thick collector
340 GHz, 70 mW amplifier design
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THz Bipolar Transistors
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1st - Order Design of Bipolar Transistors
spreading
link
contact
contact
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1st - Order Design of a 1 THz Bipolar Transistor
InP SiGe emitter 64 18? nm width 2
0.6Acont/Ajunct ???m2 access r base 60
____ nm contact width, 2.5 0.7Atotal/Acb
overlap ???m2 contact r collector 53 15 nm
thick 36 126? mA/?m2 current density 2.75
______ V, breakdown ft 1000 1000
GHz fmax 2000 2000 GHz PAs 1000 1000 GHz
digital 480 480 GHz(21 static divider metric)
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HBT Design
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Monte Carlo ? We Design HBTs By Pencil Paper (
EXCEL )
III-V HBTs remain well-modeled by
drift-diffusion equation Hand analysis predicts
quite welldevice cutoff frequencies, and logic
speed. Underlying this, we assume 3.5E7 cm/s
carrier velocity. Effective collector velocity
does not seem to increase with futher scaling.
BUT models with more precise physics are needed
to model variation of gm Ic with Vbe variation
of tf and Ccb with Ic Vce breakdown and safe
operating area thermal instability
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What Are The Challenges In Modeling ?
First-order design works quite well... But,
second-order transport physics introduces small
corrections Of greatest importance inIM3
prediction in amplifiersSimulation of mm-wave
power amplifiers
Particular attention collector current voltage
? collector velocity ? transit time , Ccb , Kirk
threshold second-order transport effects in
base-emitter junction
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HBT Physics HBT Modelling
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A comment on terminology
D. Root
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Base-Emitter Junction
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Base-Emitter Junction HBT Ic-Vbe
Characterisitics
128 64 nm scaling generation very high
Jeminority carrier concentration near, beyond
NcDEGENERATE? Fermi-Dirac, not Boltzmannroughly
modeled as series resistancebetter modeled as
Vbe (kT/q)ln(I/Is)k1I 2/3
Voltage drops in e/b depletion region--device
designers need to minimize this--to the extent
that they cannot, must model well--presently
modeled by Rseries and nkT/qI--make better
model fit to physics ?
Te0 nm
10 nm steps
Te100 nm
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Base-Emitter Junction HBT Ic-Vbe Characterisitics
E. Lind
With either graded or abrupt junctions,simple
exponential characteristics are expected? 1/gm
nkT/qIc Rex The "dip" has several
implications -we don't understand HBT
operation -we cannot extract Rex from data -so,
we can't seperately distinguish RexCcb from
tbtc -compact models fail ... right in the
high-speed bias region -confuses analysis of
"current-induced velocity modulation"
abrupt EB junction
M. Urteaga
0.5 x3 um2 Graded BE Junction
0.5 x3 um2 Abrupt BE Junction
0.6x4 um2 Abrupt BE Junction
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Base-Emitter Junction Depletion Capacitance
BE depletion capacitance--needs to be modeled
exactly in on-state (IM3 analysis) --needs to
to modeled acceptably over logic swing (ECL
CML)
The above (old ?) SPICE formalism seems
ill-suited to fitting Cje vs bias for HBTs
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Base-Collector JunctionPrimary Effects
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Collector-Base Capacitance
dipoles
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Collector-Base Capacitance
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Kirk Effect, i.e. Space-Charge-Limited Current
0 mA/mm2
10 mA/mm2
Kirk ?
Not ?
Must model boundary of Kirk threshold in
(Ic,Vce) plane. Need good RF model in
space-charge-limit
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Base-Collector JunctionSecondary Effects
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T. Ishibashi
Voltage Modulation of Collector Transit Time
With increased Vcb, electrons travel less
distance before G-L scattering
Model must incorporate some variation of
collector charge storage with voltage
H. Nakajima Japanese J. Appl. Phys., Vol. 36,
Feb. 1997, pp. 667-668
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T. Ishibashi
Current Modulation of Collector Transit Time
J0
E. Lind
J 8 mA/um2
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Transit time Modulation Causes Ccb Modulation
Camnitz and Moll, Betser Ritter, D. Root
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M. Urteaga
Transit time Modulation ? Negative Resistance ?
Infinite Gain
High extrapolated fmax in InGaAs-collector SHBTs
has been reported by several groups (UCSB,
Pohang, ...), but relevance to mm-wave amplifiers
is limited.
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Collector-base Transport Modeling Summary
Can these plots be modeled compactly, yet modeled
well ?
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Interconnects
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III-V MIMIC Interconnects -- Thin-Film Microstrip
narrow line spacing ? IC density
no substrate radiation, no substrate losses
fewer breaks in ground plane than CPW
... but ground breaks at device placements
InP mm-wave PA (Rockwell)
still have problem with package grounding
...need to flip-chip bond
thin dielectrics ? narrow lines ? high
line losses ? low current capability
? no high-Zo lines
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III-V MIMIC Interconnects -- Inverted Thin-Film
Microstrip
narrow line spacing ? IC density
Some substrate radiation / substrate losses
No breaks in ground plane
... no ground breaks at device placements
InP 150 GHz master-slave latch
still have problem with package grounding
...need to flip-chip bond
thin dielectrics ? narrow lines ? high
line losses ? low current capability
? no high-Zo lines
InP 8 GHz clock rate delta-sigma ADC
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IC design examples
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Good Kirk-Effect Models Are Essential for
ECL/CML
ECL Transistors Load Lines
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mm-wave Power Amplifiers
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mm-wave Op-Amps for Linear Microwave Amplification
UCSB / Teledyne FLARE Griffith Urteaga
Reduce distortion with strong negative feedback
2nd-generation ICs are working to design
high IP3, 40 GHz loop bandwidths
3rd-generation ICs are near completion
simulated IP3 exceeds 53 dBm ...we shall
see Accurate modeling of Ccb vs bias is
mission-critical UCSD (Tomas OSullivan, Peter
Asbeck) have been critical to effort
R. Eden
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Current IC Projects ? Modeling Challenges
340 GHz, 70 mW amplifiers (DARPA SWIFT)device
and IC layout parasiticsbreakdown safe
operating area, thermal stabilitytf and Ccb
over full signal swing
M. Jones (UCSB), J. Hacker (Teledyne)
200 GHz digital logicCcb vs (Ic , Vce)
---precise modelling of Kirk effect for low
C/IIC interconnect modelling
Z. Griffith
mm-wave op-amps? low IM3 _at_ 2 GHz Ccb vs Ic and
Vce----residual distortiongm vs Ic --- modeling
of gain, and of gm nolinearitiescompact, precise
modelling of interconnect parasitics---phase
margin !
M. Urteaga (Teledyne)
Z. Griffith
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(end)
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Backup, Sorting, etc
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First-Order HBT Design
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First-Order HBT Design