PassTransistor Logic

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Pass-TransistorLogic
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Pass-Transistor Logic
Allow inputs to drive source/drain terminals as
well as gate terminals
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Example AND Gate
Is B redundant?
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NMOS-Only Logic
Unfortunately, NMOS passes strong 0 but weak 1
(the situation is even worsened by body effect)
Avoid cascading multiple pass-logic (without
buffering)!!!
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NMOS-only Switch
V
V
does not pull up to 2.5V, but 2.5V -
TN
B
Though smaller voltage swing causes smaller
dynamic power consumption, threshold voltage loss
causes
static power consumption of following inverters
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Differential Pass Transistor Logic (DPTL)
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Properties of DPTL

• Similar to DCVSL, it accepts true and
  complementary inputs and produce true and
  complementary outputs
• Some complex gates such XORs and adders can be
  realized efficiently with a small number of
  transistors. It also eliminates the need for
  extra inverters (delay symmetric).
• DPTL is static, because the output defining
  nodes are always connected to either VDD or GND
  via low-resistance path (good for noise)
• Design is very modular, which makes designing a
  library of gates simple. More complex gates can
  be built by cascading the modules.
• Some routing overhead due to complementary
  input/output

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Robust Pass transistor logic solution 1 Level
Restoring Transistor
V
DD
V
DD
Level Restorer
M
r
B
M
2
X
M
A
Out
n
M
1
Advantage Full Swing and no static power
consumption
Restorer adds capacitance, positive on L-H
delay but negative on H-L
Ratio problem when output transitions from
H-to-L
Small for large resistance
Mr size large or small?
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Restorer Sizing
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Solution 2 NMOS Pass Gate with VT0
Zero VTN NMOS
Source-body effect might still prevent full swing
WATCH OUT FOR LEAKAGE CURRENTS!!!
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Solution 3 Transmission Gate
C
C
A
A
B
B
C
C
Can reach 2.5V and 0V
C
2.5 V
A
2.5 V
B
C
L
C

0 V
Transmission gate combines the best of both
devices by placing an NMOS in parallel with PMOS
(most popular approach). Also make circuit static.
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Resistance of Transmission Gate
It is therefore acceptable that the equivalent
on-resistance of Transmission Gate has a constant
value (8K in this case)
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Pass-Transistor Based Multiplexer
S
VDD
GND
A
B
S
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Transmission Gate XOR
When B1, M1/M2 inverter, M3/M4 off, so FAB When
B0, M1/M2 off, M3/M4 transmission gate, so FAB
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Delay in Transmission Gate Networks
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Delay Optimization
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Summary

• Ratioed logic and pass transistor logic have
  their own advantages (e.g. reduced number of
  transistors, save area, simpler implementation,
  modular design, faster)
• But they do not have the robustness and ease of
  design as the complementary CMOS (think about the
  XOR gate)
• Therefore, use them when necessary (e.g. delay,
  area)
• For designs with no extreme area, complexity or
  speed requirements, complementary CMOS is the
  recommended design style nowdays

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Dynamic Logic
Static/dynamic Ratioed/ratioless Complementary/non
-complementary
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Dynamic CMOS

• In static circuits at every point in time (except
  when switching) the output is connected to either
  GND or VDD via a low resistance path.
• fan-in of n requires 2n (n N-type n P-type)
  devices
• Dynamic circuits rely on the temporary storage of
  signal values on the capacitance of high
  impedance nodes.
• requires n 2 (n1 N-type 1 P-type)
  transistors
• Dynamic logic achieved a similar result as
  pseudo-NMOS, but avoid short circuit and static
  power consumption

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Dynamic Gate
off
on
1
Mp
Clk
Out
In1
In2
PDN
In3
off
Me
Clk
on
Two phase operation Precharge (CLK 0)
Evaluate (CLK 1)
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Conditions on Output

• Once the output of a dynamic gate is discharged,
  it cannot be charged again until the next
  precharge operation.
• Inputs to the gate can make at most one
  transition during evaluation.
• Output can be in the high impedance state during
  and after evaluation (when PDN off), this is
  fundamentally different from static complementary
  CMOS gate

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Properties of Dynamic Gates

• Logic function is implemented by the PDN only
• number of transistors is N 2 (versus 2N for
  static complementary CMOS)
• Full swing outputs (VOL GND and VOH VDD)
• Non-ratioed - sizing of the devices does not
  affect the logic levels
• Faster switching speeds
• reduced load capacitance due to lower intrinsic
  capacitance (Cin)
• reduced load capacitance due to smaller output
  loading (CL)
• no Isc, so all the current provided by PDN goes
  into discharging CL

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Properties of Dynamic Gates

• Overall power dissipation usually higher than
  static CMOS
• no static current path ever exists between VDD
  and GND (including Psc)
• higher transition probabilities
• extra load on Clk
• PDN starts to work as soon as the input signals
  exceed VTn, so VM, VIH and VIL (inverter) equal
  to VTn
• Small low noise margin (NML)
• Needs a precharge/evaluate clock

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Properties of Dynamic Gates

• Main advantage of dynamic gates are increased
  speed and reduced area.
• For low input signal, no switching occurs. So L-H
  delay 0!!
• But this neglects the influence of precharge time
  (try to coincides this time with other functions
  to improve overall performance).
• Large size of PMOS is not recommended, due to
  increased capacitance for H-L delay and clock
• For H-L, the extra evaluation transistor somewhat
  slows down the gate due to extra series
  resistance!
• Overall, the average delay is usually improved
  compared to static gates (100-150ps compared to
  200ps for 4 input NAND)

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Issues in Dynamic Design 1 Charge Leakage
CLK
Clk
Mp
Out
A
Evaluate
VOut
Clk
Me
Precharge
Leakage sources
Dominant component is subthreshold current
Requires a minimum clock rate!!
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Solution to Charge Leakage
Same approach as level restorer for
pass-transistor logic
Small or large size for keeper?
Small to avoid ratio problem
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Issues in Dynamic Design 2 Charge Sharing
Charge stored originally on CL is redistributed
(shared) over CL and CA leading to reduced
robustness
This voltage loss can not be recovered
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Charge Sharing
V
DD
M
Clk
p
Out
C
L
M
A
a
X
C
a

M
B
0
b
C

• When they are equal, it means that signal A can
  turn on both terminal of Ma
• The exact case can be determined by the
  capacitor ratio

b
M
Clk
e
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Solution to Charge Redistribution
Precharge internal nodes using a clock-driven
transistor (at the cost of increased area and
power)
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Issues in Dynamic Design 3 Backgate Coupling

• The floating high impedance of the output nodes
  makes the dynamic circuit sensitive to crosstalk
  effect ( A wire routed over or close to a dynamic
  node may couple capacitively and destroy the
  state of the node)
• The other equally important form of capacitive
  coupling is called backgate coupling (input
  coupled to output)

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Issues in Dynamic Design 3 Backgate Coupling
Clk
Mp
Out1
1
Out2
0
In
A0
B0
Clk
Me
Static NAND
Dynamic NAND
Suppose Out21 when Out11 and In0, if In goes
high, then Out2 goes low, which couples to Out1
so that Out2 could not go all the way to GND
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Backgate Coupling Effect
Due to backgate coupling
Out1
Voltage
Clk
Out2
In
Time, ns
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Issues in Dynamic Design 4 Clock Feedthrough

• A special case of capacitive coupling is clock
  feedthrough, an effect caused by capacitive
  coupling between the clock input of the
  pre-charge device and the dynamic output node.
• So voltage of Out can rise above VDD. The fast
  rising (and falling edges) of the clock couple to
  Out.
• The danger is to possibly cause revised-based PN
  junction to become forward-biased.

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Clock Feedthrough
Clock feedthrough
Clk
Out
In1
In2
In3
In Clk
Voltage
In4
Out
Clk
Time, ns
Clock feedthrough