Fast Design Space Exploration using Hierarchies

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Fast Design Space Exploration using Hierarchies

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Overview

• motivation
• ad hoc approach
• formalized approach- decomposition,
  composition- simple example- validity
  function- component level filtering- common
  /partial validity filter- quality filter-
  example

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motivation DSE in large systems

• large system design
• evaluation criteria e (cost, time)
  (performance-1)
• many design parameters (cache_size,
  cache_associativity, cache_ports,
  cpu_instruction_size)
• Problems - design space D d1,,dn is huge
  (all parameter combinations)- evaluation D ? e
  complicated (slow)- infeasible

RAM
Bus
CPU
Cache
Goal reduce number of designs to be evaluated,
with no loss in accuracy
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approach
big system
ad hoc approach
Formalizedapproach

• - split system into subsystems that interact
  little
• evaluate isolated subsystems
• recombine optimal subsystems

• Problem produces non optimal results if
  interactions between subsystems are complicated

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formalized approach

• formal method for dividing a system into
  subsystems (components), which are separately
  evaluated
• reduces design space(s) in a systematic way,
  using different filtering steps.
• only a limited number of system combinations have
  to be evaluated
• guarantees optimality of final designs (pareto
  set)

systemcomposition
system validity and optimality filtering
Component 1 Design space D1
componentfiltering
decomposition
system
...
Component n Design space Dn
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decomposition definition

• a decomposition of the design space partitions a
  system S into the components C1 ..Cn, with
• design spaces Di for all components Ci, (
  ) with different component designs di,n ,
  their evaluation functions e and a decomposition
  function, mapping a system to a set of components
• validity function V (D1X D2X Dn) ? TRUE,
  FALSEe.g. V(d1, ,di)true for a valid system
  (combination of component designs)
• composition function (D1X D2X Dn) ?
  D,, mapping all sets of component design to
  system design, or to for invalid combination

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simple, inefficient example

• no component level filtering!
• output pareto set

• Nc all combinations e.g. 10.000
• Nv valid combinations e.g. 1.000
• Np pareto comb. e.g. 100
• (start with empty pareto set, and check for
  every new valid combination, if it is dominated.
  If not, add to pareto set, and remove elements
  that are dominated)

Goal reduce Nc and Nv before final evalution, by
filtering component design space!
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Validity Function

• System Validity function V (D1D2 Dn) ?
  true, false reduced to canonical AND-OR
  formV()((a ? b ? c) v (a ? d ? e))
• Common expression term appearing in all AND
  expressions (here a)Can be factored outV()a
  ? ((b ? c) v (d ? e))
• V() CE ? PSOPCE Common Expression (a)PSOP
  Partial Sum Of Products (b?c) v (d?e)

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Component-level Filtering
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Common Validity Filter

• For each design space Di there is a common
  expression CEi (can be as simple as TRUE)
• V() is the conjunction of all CEi
• If CEi is FALSE for a design di, then V() is
  FALSE for all designs containing di
• Eliminate all di that do not satisfy CEi

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Partial Validity Filter

• V() CE ? PSOP
• PSOP ((b ? c) v (d ? e))
• CPEij Part of expression associated with
  component Ci
• Eliminate all di that do not satisfy any CPEi

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Quality Filter

• PSi is the set of designs di which satisfy CEi
  and CPEi
• Evaluate component designs di in PSi
• Choose quality (Pareto) set QSi of di
• IdeaA system design containing a component di
  in PSi but not in QSi can always be improved by
  substituting a design dp in QSi if the evaluation
  functions are perfectly correlated.

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Component-level Filtering
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Example

• Processor / mem design
• 100 designs each total Nc 10.000
• Simple System
• Validity Nv 1.000
• Quality Np 100
• Hierarchical system
• CCE 40 of 100 processors Nc 4.000
• VCPE (4 sets) 12 Proc, 50 Mem NC 2.400
• Q (4 sets) 5 Proc, 10 Mem Nc 200
• Only 200 instead of 10.000 systems have to be
  evaluated.