ECE 406 Design of Complex Digital Systems Lecture 10: 9: State Machines

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ECE 406 Design of Complex Digital
SystemsLecture 10 9 State Machines Reset
Behavior
Spring 2006 2007 W. Rhett Davis NC State
University with significant material from Paul
Franzon Bill Allen
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Summary of Lecture 8

• How do you model a flip-flop?
• What is the difference between blocking and
  non-blocking assignments?
• How do you infer flip-flops for an
  always_at_(posedge clock) procedure with blocking or
  non-blocking assignments?
• Is it better to use blocking or non-blocking
  assignments in an always_at_(posedge clock)
  procedure? Why?

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Summary of Lecture 8

• What are the key elements of the simplified
  coding stlye?
• What Verilog constructs do you use to describe
• MUXes
• Control logic
• Datapath logic
• Registers

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Todays Lecture

• State Machine Design (1.3.1, 2.6)
• Using Reset Signals (1.3.2)
• Data Converter Example

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State Machine Design

• This is a state-transition diagram
• If you were asked to design a state-machine to
  implement this diagram, how would you do it?

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Generalized State Machines

• Mealy Machine
• Most general
• outputs labeled on transitions

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Moore Machine

• Less General
• Output depends on current state only

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State Machine Design

• Step 1 Assign States
• Step 2 Create the state-register
• Step 3 Write a combinational procedure to
  implement the state-update logic and output logic

reg current_state, next_state always_at_(posedge
clock) current_state lt next_state always_at_(i
n or current_state) case (current_state)
0 if (in) next_state lt 0 else
next_state lt 1 1 if (in) next_state lt
2 else next_state lt 0 2
next_state lt 0 default next_state lt
0 endcase
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Sophisticated Style State Machine
reg state always_at_(posedge clock) case
(state) 0 if (in) state lt 0
else state lt 1 1 if (in) state lt 2
else state lt 0 2 state lt
0 default state lt 0 endcase

• Could you implement the output logic with this
  same always_at_ block?

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Todays Lecture

• State Machine Design (1.3.1, 2.6)
• Using Reset Signals (1.3.2)
• Data Converter Example

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Reset Signals

• At the start of the simulation, state has the
  value X
• What will the next state be?
• Will this be the case with synthesized hardware?

reg state always_at_(posedge clock) case
(state) 0 if (in) state lt 0
else state lt 1 1 if (in) state lt 2
else state lt 0 2 state lt
0 default state lt 0 endcase
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Rules for Reset Signals

• Only the edges for the clock and reset should be
  in sensitivity list
• Reset condition should be specified first
• No condition should be made on the clock

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Types of Reset Signals

• Asynchronous Reset happens as soon as reset
  signal is asserted
• Synchronous Reset is synchronized to clock

always_at_(posedge clock or posedge reset) if
(reset) value lt 0 else value lt next_value
Active-high reset
always_at_(posedge clock) if (reset) value lt
0 else value lt next_value
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Active-Low Reset

• How would you implement an active-low
  asynchronous reset?

WARNING Popular Exam Question!
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Resetting the State Machine
reg state always_at_(posedge clock) if (reset)
state lt 0 else case (state)
0 if (in) state lt 0
else state lt 1 1 if (in) state lt
2 else state lt 0
2 state lt 0 default state lt 0
endcase

• We generally prefer synchronous resets to
  asynchronous, so that we dont have to worry
  about the relative timing of the two signals

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Todays Lecture

• State Machine Design (1.3.1, 2.6)
• Using Reset Signals (1.3.2)
• Data Converter Example

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Data Converter Specification

• When a new 32-bit data word arrives at the input,
  the module stores it and then outputs the word as
  4 bytes, starting with the MSB and ending with
  the LSB.
• The arrival of a 32-bit word to be converted is
  signaled by a pulse on ready that is 3 clock
  cycles long.
• The output of a byte of data is signaled by a one
  clock cycle pulse on new. The output byte is
  available during the new pulse and for one clock
  cycle after.

Data Converter
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Design Process

• Step 1 Write Specification
• Step 2 Draw Schematic
• Ports
• Registers
• Datapath Logic
• MUXes
• Control Logic
• Step 3 Write Verilog Code
• Label Internal Signals
• Map elements from schematic into code

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Data Selector Schematic
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Controller State Diagram
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Data Converter (Simplified Style)

• module dataconv(IN, clock, ready, reset, OUT,
  new)
• input clock,reset,ready
• input 310 IN
• output 70 OUT
• output new

Complete the module description
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Data Converter (Simplified Style)
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Data Converter (Simplified Style)
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Data Converter (Sophisticated Style)

• module dataconv(IN, clock, ready, reset, OUT,
  new)
• input clock,reset,ready
• input 310 IN
• output 70 OUT
• output new
• reg 70 OUT
• reg new
• reg 310 value
• reg 30 state
• always _at_(posedge clock)
• begin
• if (reset)
• state lt 0

• else
• case(state)
• 0 begin
• if (ready) state lt 1
• else state lt 0
• new lt 0
• end
• 1 begin
• state lt 2
• value lt IN
• end
• 2 begin
• state lt 3
• OUT lt value3124
• new lt 1
• end

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Data Converter (Sophisticated Style)

• 7 begin
• state lt 8
• new lt 0
• end
• 8 begin
• state lt 9
• OUT lt value70
• new lt 1
• end
• 9 begin
• state lt 0
• new lt 0
• end
• default begin state lt 0 end
• endcase
• end
• endmodule

• 3 begin
• state lt 4
• new lt 0
• end
• 4 begin
• state lt 5
• OUT lt value2316
• new lt 1
• end
• 5 begin
• state lt 6
• new lt 0
• end
• 6 begin
• state lt 7
• OUT lt value158
• new lt 1
• end

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Comparison of Styles

• What will be the difference between the hardware
  synthesized from the simplified and sophisticated
  versions of the Data Converter code given in
  class?

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Summary

• How do you implement a state-machine when given a
  state-transition diagram?
• Why in general do you need a reset-signal for a
  module?
• What is the difference between synchronous and
  asynchronous reset signals?