CISC260 Machine Organization and Assembly Language

1
CISC260 Machine Organization and Assembly Language

• Lecture 7
• MIPS ISA
• Datapath Control

Adapted from slides by Dr. Mary Jain Irwin at
Penn State
2
RISC - Reduced Instruction Set Computer

• RISC philosophy
• fixed instruction lengths
• load-store instruction sets
• limited addressing modes
• limited operations
• MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel
  (Compaq) Alpha,
• Instruction sets are measured by how well
  compilers use them as opposed to how well
  assembly language programmers use them

Design goals speed, cost (design, fabrication,
test, packaging), size, power consumption,
reliability, memory space (embedded systems)
3
MIPS (RISC) Design Principles

• Simplicity favors regularity
• fixed size instructions 32-bits
• small number of instruction formats
• opcode always the first 6 bits
• Good design demands good compromises
• three instruction formats
• Smaller is faster
• limited instruction set
• limited number of registers in register file
• limited number of addressing modes
• Make the common case fast
• arithmetic operands from the register file
  (load-store machine)
• allow instructions to contain immediate operands

4
MIPS R3000 Instruction Set Architecture (ISA)
Registers

• Instruction Categories
• Computational
• Load/Store
• Jump and Branch
• Floating Point
• coprocessor
• Memory Management
• Special

R0 - R31
PC
HI
LO
5
MIPS Arithmetic Instructions

• MIPS assembly language arithmetic statement
• add t0, s1, s2
• sub t0, s1, s2

• Each arithmetic instruction performs only one
  operation
• Each arithmetic instruction fits in 32 bits and
  specifies exactly three operands
• destination ? source1 op source2
• Those operands are all contained in the
  datapaths register file (t0,s1,s2)
  indicated by
• Operand order is fixed (destination first)

6
MIPS Arithmetic Instructions

• MIPS assembly language arithmetic statement
• add t0, s1, s2
• sub t0, s1, s2

• Each arithmetic instruction performs only one
  operation
• Each arithmetic instruction fits in 32 bits and
  specifies exactly three operands
• destination ? source1 op source2

• Each arithmetic instruction performs only one
  operation
• Each arithmetic instruction fits in 32 bits and
  specifies exactly three operands
• destination ? source1 op source2

• Operand order is fixed (destination first)
• Those operands are all contained in the
  datapaths register file (t0,s1,s2)
  indicated by

7
Machine Language - Add Instruction

• Instructions, like registers and words of data,
  are 32 bits long
• Arithmetic Instruction Format (R format)
• add t0, s1, s2

op 6-bits opcode that specifies the
operation rs 5-bits register file address of the
first source operand rt 5-bits register file
address of the second source operand rd 5-bits re
gister file address of the results
destination shamt 5-bits shift amount (for shift
instructions) funct 6-bits function code
augmenting the opcode
8
MIPS Memory Access Instructions

• MIPS has two basic data transfer instructions for
  accessing memory
• lw t0, 4(s3) load word from memory
• sw t0, 8(s3) store word to memory
• The data is loaded into (lw) or stored from (sw)
  a register in the register file a 5 bit address
• The memory address a 32 bit address is formed
  by adding the contents of the base address
  register to the offset value
• A 16-bit field meaning access is limited to
  memory locations within a region of ?213 or 8,192
  words (?215 or 32,768 bytes) of the address in
  the base register
• Note that the offset can be positive or negative

9
MIPS Control Flow Instructions

• MIPS conditional branch instructions
• bne s0, s1, Lbl go to Lbl if s0?s1 beq
  s0, s1, Lbl go to Lbl if s0s1
• Ex if (ij) h i j
• bne s0, s1, Lbl1 add s3, s0,
  s1Lbl1 ...

• Instruction Format (I format)

• How is the branch destination address specified?

10
Specifying Branch Destinations

• Use a register (like in lw and sw) added to the
  16-bit offset
• which register? Instruction Address Register
  (the PC)
• its use is automatically implied by instruction
• PC gets updated (PC4) during the fetch cycle so
  that it holds the address of the next instruction
• limits the branch distance to -215 to 215-1
  instructions from the (instruction after the)
  branch instruction, but most branches are local
  anyway

11
Adding the Control

• Selecting the operations to perform (ALU,
  Register File and Memory read/write)
• Controlling the flow of data (multiplexor inputs)

31
25
20
15
5
0
10
R-type
op
rs
rt
rd
funct
shamt
31
25
20
15
0

• Observations
• op field always
  
  in bits 31-26
• addr of registers
  
  to be read are
  
  always specified by the
  
  rs field (bits 25-21) and
  rt field (bits 20-16) for lw and sw rs is the
  base register
• addr. of register to be written is in one of two
  places in rt (bits 20-16) for lw in rd (bits
  15-11) for R-type instructions
• offset for beq, lw, and sw always in bits 15-0

I-Type
address offset
op
rs
rt
12
(vonNeumann) Processor Organization

• Control needs to
• input instructions from Memory
• issue signals to control the information flow
  between the Datapath components and to control
  what operations they perform
• control instruction sequencing

CPU
Memory
Devices
Control
Input
Datapath
Output

• Datapath needs to have the
• components the functional units and
  storage
  (e.g., register file) needed to execute
  instructions
• interconnects - components connected so that the
  instructions can be accomplished and so that data
  can be loaded from and stored to Memory

13
Single Cycle Datapath with Control Unit
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
14
R-type Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
15
Load Word Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
16
Load Word Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
17
Store word instruction Data/Control Flow
18
Branch Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
19
Branch Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
20
Adding the Jump Operation
Instr25-0
1
Shift left 2
32
28
26
0
PC431-28
0
Add
Add
1
4
Shift left 2
PCSrc
Jump
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0