FPGA Architecture Evaluation and Technology Mapping using Boolean Satisfiability

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FPGA Architecture Evaluation and Technology
Mappingusing Boolean Satisfiability

• Andrew Ling M.A.Sc Candidate
• (University of Toronto)
• Deshanand P. Singh Ph.D.
• Valavan Manohararajah Ph.D.
• Professor Stephen D. Brown
• (University of TorontoAltera Corporation -
  Toronto Technology Centre)

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Applications of SAT to FPGAs

• FPGA Routing (G. Nam et al. VLSID, 1999)
• Sliding Window Resynthesis
• PLB (Programmable Logic Block) technology mapping
• Verification of PLB Robustness

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FPGA
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K-LUT
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Background LUT Mapping Problem

• Given a subject graph representing the circuit
  (usually a netlist of 2-input gates)
• Want a covering of the graph using LUTs.
• Equivalently - Want a covering of the graph
  using cones.

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Cone

• A subgraph consisting of a root node and its
  predecessors such that any node within the cone
  has a path to the root that lies entirely within
  the cone.
• Constraint on the number of unique inputs (K).
• Cone K-LUT.

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LUT Mapping Problem
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LUT Mapping Problem
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LUT Mapping Problem
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Cone Selection

• Depth-oriented mapping
• Select the cones that guarantees the smallest
  depth.
• Area-oriented mapping
• Select the cones that cover the most gates per
  cone.

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Satisfiability-based Technology Mapping (SATMAP)
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K-Input PLB

• The 3-input PLB below CANNOT implement any
  arbitrary 3-input function

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K-Input PLB
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K-Input PLB
SAT ?
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Deriving Characteristic FunctionT. Larrabee,
Test pattern generation using Boolean
satisfiability," TCAD, 1992 (Plaisted's and
Greenbaum's encoding which is based on Tseitin's
work)
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Extending to Larger Circuits
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SAT applied to PLBs
?

• Can function f be implemented in circuit g ?
• Does there exist a configuration to g such that
  for all inputs to g, f is equivalent to g

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SAT applied to PLBs
?

• Derive characteristic function H for circuit g
• Replace all instances of g in H with f,
  Hg/f (g f )

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SAT applied to PLBs
?

• Express as a QBF with inputs (x1xn) and
  configuration bits (l1lm)
• l1lm x1xn (g f )
• Remove quantifiers to form a SAT problem (A.
  Biere. Resolve and Expand, SAT04)

A
E
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Evaluating PLBs

• Extract set of k-Input Cones from a large set of
  circuits.
• Examine the percentage of cones fit into PLB
  structure.

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Evaluation of PLBs
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Applying SAT to Techmapping

• Use any existing k-LUT techmapper and apply SAT
  verification step in addition k-LUT feasibility.
• We use IMAP (V. Manohararajah Technology Mapper)
  in our experiments.

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Technology Map to the Apex20k PLB
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Applied to Techmapping

• Depth-Oriented Techmapping using the Apex20K PLB.

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Applied to Techmapping

• Area-Oriented Techmapping using the Apex20K PLB

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Conclusions

• Novell function mapping technique based on
  Boolean satisfiability
• Introduced method to incorporate SAT into
  technology mapping
• Introduced a PLB evaluation method

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Future Work

• Speed up SAT, use QBF solvers, ALL-solution SAT
  solvers
• Cannot evaluate area efficiency without looking
  at routing architecture
• Use Dont Cares when mapping functions
• Use genetic algorithms to create candidate PLBs,
  then pipe architectures to our PLB evaluator tool

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Questions?