ELEC 5270-001/6270-001 Spring 09 Low Power Design of Electronic Circuits

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ELEC 5270-001/6270-001 Spring 09 Low Power
Design of Electronic Circuits

• VLSI Synthesis and Simulation Tools
• Nitin Yogi 01/09/2009

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X-Win32

• X-Win32 is used to log into UNIX session
• Use Windows Auburn login and password to log into
  X-Win32 session.

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Start X-Win32 from here
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Windows Security Alert Warning
If Windows Security Alert window pops up, press OK
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X-Win32 Login Screen
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Sometimes X-Win32 may hang at this screen
Right-click on the X-Win32 icon in the task-bar
and click X-Config
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When X-Win32 doesnt load
Click on Engineering and then click on Remove.
Then restart X-Win32
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You might also get this screen
Double click on Scan for Unix/Linux hosts
Click on any of the server names and click on
Select
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You might also get this screen
Click OK
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UNIX session

• Setup the softwares required to run the tools for
  simulation, synthesis and test
• At the command prompt type the following command
  and hit Entergtgt user-setup

Command prompt to type commands in
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User Setup screen
Click on button Electronics Data Analysis (EDA)
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User Setup screen
3. Click the X button on the top right
2. Click on the following software
packageseda/Modelsim/6.4 eda/ICFlow/2007.2 eda/D
FT/2007.3
1. Go to the bottom of the option screen
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Click on Save and Quit
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The Added modules will be displayed here
Press Commit Changes
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X-Win32 reset

• Exit X-Win32 and restart the X-Win32 session
  again as described earlier

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UNIX environment

• When you log-in into X-Win32, the current default
  directory is the H of windows system
• Some useful UNIX commands
• gtgt cd ltdirectory_namegt change directory
• gtgt cd .. go up one directory
• gtgt ls list contents of directory
• gtgt pwd display the full path of the current dir.
• gtgt mkdir create directory

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Designing, compiling and simulating designs

• In the current design directory (where your HDL
  file resides) run the following commands
• gtgt vlib work
• gtgt vmap work work
• To simulate any design, you need to compile your
  design first. Compile your VHDL design using the
  commandgtgt vcom ltVHDL filenamegte.g.gtgt vcom
  my_ckt.vhd
• ModelSim tool is used for simulating the
  designTo invoke ModelSim, use the following
  commandgtgt vsim ltdesign_namegte.g.gtgt vsim
  my_ckt
• Note vsim command takes the design name as the
  input and not the HDL file

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1. Click on View gt List to select it (displayed
as a tick)
2. Click on View gt Objects to select it
(displayed as a tick)
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Right click the input signal name and then click
Force
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Enter the value of the signal over here and then
click OK
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To simulate, click Simulate gt Run gt Run 100
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Useful resource

• VHDL Design and Simulation using ModelSim on
  Prof. Nelsons website
• http//www.eng.auburn.edu/department/ee/mgc/quickv
  hdl/modelsim.html

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From Prof. Nelsons slides
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From Prof. Nelsons slides
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Synthesis

• We shall use the tool Leonardo to synthesize the
  behavioral description into structural level
  netlist
• Command to invoke Leonardo isgtgt leonardo

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Click on LeonardoSpectrum Level 3 and then click
OK
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Click on Advanced FlowTabs
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Select the library and then click on Load
Library
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Select your HDL file by clicking Open files
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Current selected designs will be displayed in
this list
Click on the Read button to read the current
selected HDL design(s) into the tool
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Area or Delay optimization of circuit can be
selected from here
Click Optimize to synthesize the circuit
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Report Area gives the types and number of gates
used
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Report Delay gives the critical path and its
delay
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Enter a name for the output file and select the
format.
Click Write to write the synthesized design to
file
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Preparing for simulation of synthesized netlist
(Verilog format)

• Compile the gate designs that will be used by
  your Verilog synthesized netlist
• The gate designs are in a file named adk.vhd at
  the location ADK/technology
• Type the following command in your current
  working directory gtgt vcom ADK/technology/adk.vh
  d -work ./work/
• Compile Verilog netlist
• gtgt vlog ltVerilog file_namegte.g. gtgt vlog
  my_ckt.v
• Simulate Verilog design using ModelSim
• gtgt vsim ltdesign_namegte.g.gtgt vsim my_ckt

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Commands for Analogue Simulation

• Analogue simulation set-up commands
• gt ana
• gt setenv MGC_IC_GENERIC_LIB /opt/mentor/ICFlow/200
  7.2/mgc_icstd_lib/generic_lib/
• gt setenv ADK_TECH tsmc018
• gt setenv MGC_AMS_HOME /opt/mentor/anacad/
• gt unlimit
• Design architect invocation command
• gt da_ic

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Import Verilog Netlist
File gt Import Verilog
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Import Verilog netlist (cont.)
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Open Imported Netlist
To open imported netlist click on Schematic
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Click on Simulation to enter simulation mode
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Setup analogue simulation environment
Click on Lib/Tmp/Inc gt Libraries
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Setup analogue simulation environment (Libraries)
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Power Supply (VDD) specification file
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Setup analogue simulation environment (Analyses)
Click on Analyses
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Setup analogue simulation environment (Analyses)
Click on Transient gt Setup
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Setup analogue simulation environment (Forcing
signals)
Click on the signal and then click on Forces gt Add
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Setup analogue simulation environment (Forcing
signals)
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Setup analogue simulation environment (Forcing
signals)
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Setup analogue simulation environment (Forcing
signals)
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Files generated by DA_IC
From Prof. Nelsons slides
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Working directory of DA_IC
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Force file generated by DA_IC
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Setup analogue simulation environment
(Measurements)
Click on Measurements gt Define
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Setup analogue simulation environment
(Measurements)
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Setup analogue simulation environment
(Measurements)
Click on Measurements gt Edit
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Setup analogue simulation environment
(Measurements)
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Run Simulation
Click on Netlist and then Run ELDO
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Wave Viewer (EZWAVE)

• Invoke EZWAVE using the command
• gtgt ezwave
• Note Ensure the UNIX commands to set-up the
  analogue simulation environment (e.g. ana, setenv
  etc. ) are executed before invoking ezwave

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EZWAVE window
Click on Open button to open a waveform database
file (.wdb)
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Probed Signals will be loaded here.Drag and drop
the required signals in the right-hand side
waveform window.
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