MGPA design review

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• MGPA design review
• architecture overview and specifications
• detailed architecture
• top level functional block diagram
• CSA stage
• VI stage
• Differential O/P stage
• CAL circuit
• noise sources and simulations
• process simulations whole circuit (including
  power supply 10, temperature variations)
• linearity
• pulse shape matching
• gain
• noise
• I/P interface
• input APD, VPT (transmission line effects)
• power and PSR
• miscellaneous issues bond lead inductance,
  protection, layout

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MGPA specifications
Parameter Barrel End-Cap
fullscale signal 60 pC 16 pC
noise level electrons 10,000 electrons 3,500 electrons
noise level C 1.6 fC 0.56 fC
input capacitance 200 pF 50 pF
output signals to match ADC differential 1.8 V, /- 0.45 V around Vcm (Vdd-Vss)/2 1.25 V differential 1.8 V, /- 0.45 V around Vcm (Vdd-Vss)/2 1.25 V
gain ranges 1, 6, 12 1, 6, 12
gain tolerance (each range) /- 10 /- 10
linearity (each range) 0.1 fullscale 0.1 fullscale
pulse shaping (impulse response) 40 nsec CR-RC 40 nsec CR-RC
channel/channel pulse shape matching lt 1 lt 1
Vpk-25ns
Vpk
Vpk-25ns/Vpk matches to 1 across gain ranges
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MGPA architecture overview
V/I gain resistors
external components define CR and CSA gain
diff. O/P
external components define RC
offset adjust
offset CAL pulse generation
I2C interface
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CSA I/P stage conventional folded
cascode maximise use of available dynamic range
resistor to VDD -gt I/P device Vs 1V
gt I/P and O/P as close as poss. to VSS
note output -gt PMOS source followers with
0.5V VGS ext. components define gain and O/P
decay time (40 ns) choose to suit
barrel/endcap Cpf/Rpf 33pF/1.3k
(barrel) or 10pf/4k (endcap) gt max
signal accommodated ( 1V) with min.
pile-up input device dimensions big gm
needed for low O/P risetime (Cdet200pF)
30,000/0.36 -gt Cgs 60 pF, gm.3A/V bias current
magnitudes (externally defined) for big
I/P device gm (see above) slew rate at
output node bias transistor dimensions
avoid minimum length keep gm low (noise)
but need low Vdsat
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CSA O/P simulation (barrel case) nominal process
parameters Cpf/Rpf 33pF/1.2k input
capacitance 200 pF signal injected at 25 ns
0 -gt 60 pC in 2pC steps 10 ns
arrival time to simulate scintillation decay
time resulting pulse peaks at 47 ns (22ns
injection -gt pk) 1.1 Volt max amplitude swing
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CSA O/P simulation (end-cap case) Cpf/Rpf
10pF/4k input capacitance 50 pF signal injected
at 25 ns 0 -gt 16 pC in 1pC steps
10 ns arrival time to simulate scintillation
decay time resulting pulse peaks at 48 ns
gt 23ns injection -gt pk 1.0 Volt
max amplitude swing CSA O/P pulse shape
independent of whether barrel or endcap
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range Rgain ohms Ibias mA
high 17 22
mid 41 16
low 240 9
VI stage design choices governed by linearity,
noise considerations, supply current
requirements (not excessive), need to produce
current output (high O/P impedance) to drive
diff. O/P stage Rgain gives good linearity
acceptable noise (later) s.f. and cascode
currents all derived from one current
source cascode gate voltage derived from preamp
I/P ensures minimum DC voltage across
Rgain s.f. and cascode widths and drain currents
for large gm (note Rgain values relatively
small) IDS different for different gain
stages chosen to get linearity within
spec. trade-off linearity/power
RC coupled (external)
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2.2V
source follower O/P
cascode O/P
VI stage simulation waveforms (nominal process
parameters) low gain channel signal 0 -gt 60 pC
in 6 pC steps
1.1V
cascode I/P
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Differential O/P stage single ended current in
-gt differential current out
ADC I/P signal range /- 0.45 V
around Vcm (1.25V) O/P RC termination sets
shaping time const. 200 ohms compromise
between low-ish O/P impedance and DC
quiescent current 40 nsec requires 100
pF differential (2.5 pF/nsec) or 200
pF each O/P to Vcm (5 pF/nsec) programmable
offset adjust to each channel
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Lowest gain channel differential O/P stage
signals signals 0 60 pC, 2 pC steps
VCM 1.25 V
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Higher gain channels saturation effects (still
0 60 pC, 2 pC steps)
highest gain range
middle gain range
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MGPA output (out) (out-)
0 60 pC, 2 pC steps highest (red) and mid
(blue) gain ranges saturate lowest (green)
well-behaved
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CAL circuit
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CAL circuit simulation
MGPA I/P
10pF
DAC value e.g. 100mV
10k
Rtc
Rtc0 -gt10W
1nF
external components
Highest gain channel O/P for 1 pC input
signal Can use Rtc to simulate real signal
risetime
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Noise
Rpf
diff. O/P gain stage
transconductance gain stage
vRpf2
CI
Cpf
iCFET2
s.f.
RG
RI
vFET2
CIN
charge amp.
VCM
iRG2
ENC due to charge amp. noise sources Rpf
note Rpf constrained by Cpf (RpfCpf t
2RICI 40 nsec. ) -gt 4900 electrons
(barrel) -gt 2700 electrons (endcap) I/P
FET (CTOT CIN CFET Cpf) -gt 1800
electrons (barrel, CIN300pF (200 60
40)) -gt 660 electrons (endcap, CIN112pF (40
60 12)) gtno strong dependence on CIN
1/2
K1t Rpf
K2vFETCTOT t
1/2
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Noise
Rpf
diff. O/P gain stage
transconductance gain stage
vRpf2
CI
Cpf
iCFET2
s.f.
RG
RI
vFET2
CIN
charge amp.
VCM
iRG2
ENC due to transconductance stage sources RG
-gt Cpf dependence
because relative magnitude depends on
charge amp gain. Keep RG as small as poss. but
has to vary for different gain
stages Cascode FET -gt Cpf and RG
dependence V/I stage noise sources become more
important for lower gains (bigger RG)
1/2
RG t
K3Cpf
1/2
gm t
K4CpfRG
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Simulated noise dependence on gain
Gain RG signal range (barrel) pC Noise (barrel) electrons signal range (endcap) pC Noise (endcap) electrons
12 14 0 5 6200 0 1.33 2700
6 34 5 10 8200 1.33 2.67 3073
1 240 10 - 60 35,400 2.67 16 9800
these results are for final gain range spec. (1,
6, 12), nominal process parameters and VDD,
T gain resistor noise dominates for lowest gain
range numbers in red exceed 10,000 (3500) but
signal size means relative contribution to
overall energy resolution less significant (see
http//www.hep.ph.ic.ac.uk/dmray/pptfiles/Ecalpro
g2.ppt)
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Process and environment simulations Process
parameters sigma (length,VT) 0, /- 1.5 np
mismatch nom, /- 3 sigma values Supply
Voltage (/- 5) 2.375, 2.5, 2.625(not yet
done) Temperature -10, 25, 75 simulation
results here for 1, 5, 10 gain ratios (not latest
1, 6, 12) simulations transient signals 0
-gt fullscale in 10 steps, for each gain range
look at linearity linearitylt 0.1
fullscale pulse shape matching
Vpk-25ns/Vpk matches to 1 for all
signals within gain ranges across gain
ranges noise gain
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simulation example signals 0 -gt fullscale in
10 steps for all 3 gain ranges for a given set
of process parameters and environment variables
(VDD, T) look for linearity within gain
ranges (/- 0.1 fullscale) 6 pC, 12 pC, 60 pC
pulse shape matching for all sizes of
signals within gain ranges and across
gain ranges (/- 1)
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Linearity results VDD 2.5V, T25
Linearity definition peak pulse ht. fit (to
pk pulse ht) X100 fullscale
signal results here for sigma -1.5, 0,
1.5 np mismatch -1, 0, 1 27 curves 9 for each
gain range
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Linearity results VDD 2.375V (- 5), T25
results here for sigma np mismatch 0
0 -1.5 -1 1.5 -1 -1.5 1 1.5
1 15 curves 5 for each gain range
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Linearity results VDD 2.375V (- 5), T75
results here for sigma np mismatch -1.5
-1 1.5 -1 -1.5 1 1.5 1 12
curves 4 for each gain range
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Linearity results VDD 2.375V (- 5), T-10
results here for sigma np mismatch -1.5
-1 1.5 -1 -1.5 1 1.5 1 12
curves 4 for each gain range
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Pulse shape matching results VDD 2.5V, T25
Pulse shape matching definition Pulse Shape
Matching Factor PSMFV(pk-25ns)/V(pk) Ave.PS
MF average for all signal sizes and
gain ranges, for a particular
set of process parameters
Pulse shape matching
(PSMF-Ave.PSMF)/Ave.PSMF X 100 results here
for sigma -1.5, 0, 1.5 np mismatch -1, 0,
1 27 curves 9 for each gain range
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Pulse shape matching results VDD 2.375V (-
5), T25
results here for sigma np mismatch 0
0 -1.5 -1 1.5 -1 -1.5 1 1.5
1 15 curves 5 for each gain range
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Pulse shape matching results VDD 2.375V (-
5), T75
results here for sigma np mismatch -1.5
-1 1.5 -1 -1.5 1 1.5 1 12
curves 4 for each gain range
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Pulse shape matching results VDD 2.375V (-
5), T-10
results here for sigma np mismatch -1.5
-1 1.5 -1 -1.5 1 1.5 1 12
curves 4 for each gain range
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gain dependence on process params histogram peak
pulse heights for fullscale (6 pC) signal for
highest gain range other gain ranges behave
similarly
VDD2.5V, T25
VDD2.375V, T25
VDD2.375V, T75
VDD2.375V, T -10
peak pulse height for 6 pC signal V
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histogram noise dependence on process params, VDD
T
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End-cap VPT interface
coax
I(t)
CSA O/P
Cdet
MGPA
I(t) current source with 10 ns decay time Cdet
5 pF (2 pF stray) coax RG 179 (thin 50 ohm)
75 cm long some ringing observable at CSA
O/P smoothed out at chip O/P
chip O/P
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Barrel APD interface
coax
I(t)
CSA O/P
Cdet
MGPA
I(t) current source with 10 ns decay time Cdet
160 pF (2 APDs) coax RG 179 (thin 50 ohm) 30
cm long some ringing observable at CSA O/P once
again smoothed out at chip O/P would be better
to have more accurate interconnection model
chip O/P
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Power consumption _at_ 2.5 V Stage current
mA bias cct no. powermW CSA 40 4 1 110 H
igh gain VI 44 2.2 1 116 Mid-gain
VI 32 1.6 1 84 Low gain VI 18 0.9 1
47 Diff O/P 18 1.5 3 146 Total 503
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PSR rejection - preliminary
swept frequency sine-wave superimposed on
VDD resulting output on high gain channel
O/P (out) (out-) high frequency rejection
due to RC filtering of power rail (RC 1W x
10mF) some rejection at DC but gain at 100
Hz
0 dB
-20 dB
-40 dB
-60 dB
1
100
10k
1M
Hz
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PSR rejection improvement
0 dB
replace resistor to rail biasing by ideal
current sources (CSA and VI stages) 100 Hz
bump removed DC rejection the same more
detailed study needed here hope for further
improvement
-20 dB
-40 dB
-60 dB
1
100
10k
1M
Hz
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Any effect of bond-wire inductance? model
by inserting inductances between external
decoupling and internal circuit nodes
L0,2,4,6 nH high gain range signal 5
pC effect just visible no sig. effects on
performance
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Conceptual layout
80 pin package may -gt 100 CAL circuit
included spare pins available for I2C
test reset extra power segmented
approach minimise crosstalk between
different gain stages multiple power pads all
bias lines decoupled diff. O/Ps separated
layout (chip and hybrid) needs care
different stray capacitance -gt different
pulse shapes/gain range) internal gain resistor
/- 10 tolerance
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MGPA specifications review
Parameter Barrel End-Cap
fullscale signal 60 pC 16 pC
noise level electrons 10,000 electrons 3,500 electrons
noise level C 1.6 fC 0.56 fC
input capacitance 200 pF 50 pF
output signals differential 1.8 V, /- 0.45 V around Vcm (Vdd-Vss)/2 1.25 V differential 1.8 V, /- 0.45 V around Vcm (Vdd-Vss)/2 1.25 V
gain ranges 1, 6, 12 1, 6, 12
gain tolerance (each range) /- 10 /- 10
linearity (each range) /- 0.1 fullscale /- 0.1 fullscale
pulse shaping (filtering) 40 nsec CR-RC 40 nsec CR-RC
channel/channel pulse shape matching lt 1 lt 1
OK for mid and high gain ranges (low gain not a
problem)
need to tweak
technology spec. for resistors used
OK
OK
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Outstanding issues tweak the gain resistor
values (trivial - dont expect any adverse
consequences) choose CAL circuit DAC resistor
values (trivial) PSR could adjust CSA, VI
stage bias cctry to improve (needs some
thought) needs to be supply independent use
bandgap or VT referenced current
sources (existing designs) channel offset
generation make supply independent check O/P
stage in conjunction with ADC I/P stage (should
be done)