Adaptive Hardware Design for Digital Signal Processing

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Adaptive Hardware Design for Digital Signal
Processing

• Advisor Dr. Thomas L. Stewart
• By
• Prabjot Kaur
• Alex Tan

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Presentation Outline

• Project Goal
• Applications
• Project Description
• Functional Description
• Block Diagram
• Datasheet
• Preliminary Work
• Design Approaches
• Equipment List
• Schedule

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Project Goal

• Design a Digital Signal Processing (DSP) hardware
  device
• Implemented With Field Programmable Gate Arrays
  (FPGAs).
• Investigate the capability of FPGAs to perform
  different functions through reconfigurations of
  the hardware design.
• VHDL/Xilinx Software package.

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Applications

• Configurable Computing
• Automatic Target Recognition (ATR)
• UCLA Mojave Project
• Single Chip Multitasking Solutions
• UCLA Electrical Engineering Department
• Cryptography
• High Speed Image Processing

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Project Description

• Functional Description
• DSP is the process of manipulating a digital
  input. This process utilizes multipliers and
  adders to achieve this.
• Typical Equation
• y(n) a1y(n-1)a2y(n-2)......amy(n-m)bx(n)

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Project DescriptionFunctional Description contd.

• x(n) 8 or 16 bit 2s complement word
• Control Switch Precision of the DSP function to
  be implemented
• y(n) The result of the DSP function.

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Project DescriptionFunctional Description contd.

• y(n) a1y(n-1)a2y(n-2)......amy(n-m)bx(n)
• I/P signal will be multiplied with a constant and
  added to the previously amplified O/P thus
  producing the current output signal.
• Designed to have the capability of adapting
  itself to different inputs and thus performing
  the function accordingly.
• Depending on the I/P signal device will change
  its internal configuration to produce an
  appropriate output.
• Determination of which DSP function to be
  implemented is decided by the control signal.

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Project DescriptionBlock Diagram
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Project DescriptionBlock Diagram contd.
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Project DescriptionDatasheet

• Xilinx XC4000E series.

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Project DescriptionDatasheet

• Xilinix XC4000E series.

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Project DescriptionDatasheet

• Xilinix XC4000E series.

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Preliminary Work

• Research
• Xilinx Web-site
• Learning Xilinx software (Schematic Capture)
• VHDL Software Language

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Preliminary Work

• Research digital circuitry for
• Multiplier
• Adder
• Memory Cells
• Research hardware capabilities

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Preliminary Work

• Multiplier
• Booths Algorithm
• High Speed
• 2s Complement numbers

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Preliminary Work

• Adder

A B Y
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Preliminary Work
Memory Cell
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Preliminary Work

• Built and simulated an XOR Gate using Xilinx
  schematics
• Researched hardware specifications for the
  XC4000E series

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Design Approaches

• Build and test an 8-bit and 16-bit multiplier and
  adder
• Build and test memory cells and registers
• Complete an 8-bit and a 16-bit DSP chip
• Reconfigure the FPGA between real time 8-bit and
  16-bit DSP processing

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Equipment List

• Xilinxs XC4000E Chip with board
• A/D and D/A converters
• RAM

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Schedule

• Work Time Jan. 24 - April 15, 2000
• Four main parts
• 2 weeks Research and Learning
• 3 weeks Design and Building (more emphasis on
  Design)
• 3 weeks Design and Building (more emphasis on
  Building)
• 3 weeks Testing and recording Data
• Time after April 15 Testing and getting ready
  for demo.

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Thank You!

• Any Questions?