Asynchronous FSM

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Asynchronous FSM

• ECE-331, Digital Design
• Dr. Ron Hayne
• Electrical and Computer Engineering

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Synchronous FSM Assumptions

• Single-Clock Property
• There is one, distinguished input called the
  clock
• Output changes and state changes occur only in
  response to the clock input
• No input other than the clock directly affects
  the output
• Single Edge Property
• All internal state changes occur in response to a
  single edge or level of the clock

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Asynchronous FSM

• Fundamental Mode Assumption
• An output change does not depend on the
  simultaneous change of more than one input
• Fundamental Mode Operation
• Only one input is allowed to change at a time
• FSM is allowed to settle to a stable state before
  a next input is allowed to change

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Asynchronous FSM
Input
Next State Variables
Present State Variables
Feedback
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Asynch. Design Difficulties

• Delay in Feedback Path
• Not reproducible from implementation to
  implementation
• Variable
• may be temperature or electrical parameter
  dependent within the same device
• Analog
• not known exactly

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Asynch. FSM Benefits

• Fastest FSM
• Economical
• No need for clock generator
• Output Changes When Signals Change, Not When
  Clock Occurs
• Data Can Be Passed Between Two Circuits Which Are
  Not Synchronized

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Analysis of Asynch. FSM, e.g.
Input
Next State
y1
Present State
y2
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Next State Variables
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K-Map of NS Variables
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Transition Table
NS Y1Y2
grey code
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Stable State

• PS NS Stability
• Machine may pass through none or more
  intermediate states on the way to a stable state
• Desired behavior since only time delay separates
  PS from NS
• Oscillation
• Machine never stabilizes in a single state

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Stable States
NS Y1Y2
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State Diagram
0
0
00
01
0
1
1
1
Oscillation
10
11
1
0
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Races

• A Race Occurs in a Transition From One State to
  the Next When More Than One Next State Variables
  Changes in Response to a Change in an Input
• Slight Environment Differences Can Cause
  Different State Transitions to Occur
• Supply voltage
• Temperature, etc.

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Races
PS
01
10
desired NS
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Types of Races

• Non-Critical
• Machine stabilizes in desired state, but may
  transition through other states on the way
• Critical
• Machine does not stabilize in the desired state

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Critical vs Non-Critical Races
PS
01
10
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Analysis of Transition Table

• Starting From Each Stable State, Determine If a
  Change in Any Input Variable Causes a Change in
  More Than One State Variable

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Normal State Transition
Assume PS00
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Normal State Transition

• Input Variable Changed From 0 to 1
• PS Changed From 00 to 10
• Only one state variable changed, so no race
• 10 Turned Out to Be a Stable State When Input
  Equals 1
• No other states transited on way to stable state
• Note that input determines column in which to
  find PSNS

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Race Transition
Assume PS10
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Race Analysis
PS
10
01
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Another Example
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Stable States
PS NS Stability
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Identify Races
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Race Analysis (1)
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critical
00
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Race Analysis (2)
10
01
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Cycles to Avoid Races
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End of Lecture

• Asynchronous FSM
• Fundamental Mode Assumption
• Analysis of Async FSM
• Stable States
• Normal Transition
• Races