Parallel FIR implementation - PowerPoint PPT Presentation

1 / 13
} ?>
View by Category
About This Presentation
Title:

Parallel FIR implementation

Description:

Can be clocked at up to 193MHz. worst case conditions. full result available in a single cycle ... Total gates = 49,400 No pipeline, 171MHz clock ... – PowerPoint PPT presentation

Number of Views:36
Avg rating:3.0/5.0
Slides: 14
Provided by: DublinV
Learn more at: http://grouper.ieee.org
Category:

less

Write a Comment
User Comments (0)
About PowerShow.com