A HighSpeed Hardware Implementation of the LILIII Keystream Generator Paris Kitsos '''in cooperation

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A High-Speed Hardware Implementation of the
LILI-II Keystream GeneratorParis Kitsos ...in
cooperation with Nicolas Sklavos and
Odysseas Koufopavlou

• Digital Systems and Media Computing Laboratory
• School of Science Technology
• Hellenic Open University, Patras, Greece
• e-mail pkitsos_at_ieee.org

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Presentation Overview

• LILI-II specifications overview
• Proposed hardware architecture
• VLSI implementation results
• Comparisons in terms of FPGA area, clock
  frequency and performance with existing works

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LILI-II Specifications (I)

• LILI-?? generator is a clock-controlled nonlinear
  filter generator
• LILI-II
• Use two binary LFSRs and
• Two functions in order to generate a pseudorandom
  binary keystream sequence
• The components of LILI-II grouped into two
  subsystems, based on the functions they perform
• Clock control and Data generator

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LILI-II Specifications (II)

• The LFSR for the clock-control subsystem is
  regularly clocked
• The output of the Clock-Control LFSR control the
  Data-Generation LFSR

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LILI-II Specifications (III)

• Clock-control LFSR (LFSRc)
• Use a primitive polynomial with length equal to
  128
• The function fc defined as
• Data Generation LFSR (LFSRd)
• Use a primitive polynomial with length equal to
  127
• The Boolean function fd has 12 inputs for the
  LFSRd stages and defined by a truth table

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Proposed Architecture (I)

• The proposed architecture consists of the
  clock-control subsystem and the data generation
  subsystem
• Operation
• Initialization phase
• Keystream generation phase
• Initialization Phase
• Use the secret key and initialization vector and
  operates twice and the output feeds the LFSRs as
  new values
• Keystream generator Phase
• When the initialization phase finish the
  generator produce the appropriate keystream bits.

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Proposed Architecture (II)
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Proposed Architecture (III)

• The Clock-Control subsystem is comprised by the
  LFSRc, the function fc and the Clock Pulses
  components.
• The fc is a simple 3-bit adder.
• The Clock Pulses control the LFSRds through the
  AND gates.

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Proposed Architecture (IV)

• The Data-Generation subsystem is comprised by 4
  LFSRds, 4 AND gates, the function fd, 6 Pipeline
  Registers and 12 4x1 Multiplexers.
• Pipeline registers are located in the LFSRd(i)
  outputs in order to equalise the data delays
  between of them
• The multiplexers (MUXs) are used in order to
  combine the appropriate LFSRds positions
• The fd function is implemented by ROM with 4096
  per 1-bit elements

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A Different Approach

• Many applications, in the same device, demand
  different security levels. This could be achieved
  with the usage of reconfigurable LFSRs, if
  different feedback polynomials selected any time.

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VLSI Implementation Results
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Comparisons
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Conclusions

• An efficient hardware implementations of the
  LILI-II keystream generator was presented
• Achieves a throughput equal to 366 Mbps
• The proposed architecture is more hardware
  efficient than previous works

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• Questions ?