Finite State Machines in Verilog

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Finite State Machines in Verilog
CS 153, Spring 2007 Ian G. Harris Department of
Computer Science University of California Irvine
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FSM Implementations

• FSM could be implemented structurally, but
  behavioral is better

11 Detector - Detects a 11 sequence on input w
reset

• Moore machine - Output depends on state, not
  inputs
• Output is z, inputs are w and reset
• Z set to 1 when 11 occurs on input w

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Moore Machine Structure
inputs
outputs
Current state

• Verilog code will have this structure as well

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FSM Verilog, Next State Logic
module one_one_det (Clock, Resetn, w, z) input
Clock, Resetn, w output z reg 21 y,
Y parameter 21 A2b00, B2b01,
c2b10 always _at_(w or y) case (y) A
if (w) YB else YA B if (w) YC
else YA C if (w) YC else
YA default Y2bxx endcase

• Each state is a branch of the case
• Each transition is a branch of an if

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Alternative Next State Logic
always _at_(w or y) if (!w) Y A else
case (y) A YB B YC C
YC default Y2bxx endcase

• Why is this different from the original
  definition?

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FSM Verilog, State Elements and Output Logic
always _at_(negedge Resetn or posedge Clock) if
(Resetn 0) yltA else yltY assign z
(yC)
Alternative for Output Logic
always _at_(y) if (y C) z 1 else
z 0