PHOS FEE an overview

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PHOS FEE an overview
PHOS Front-End Electronics, Sep. 2003

• Highlights
• Requirements and milestones
• PHOS FEE topology
• Energy, Timing, Trigger and Control
• Road map and main engineering tasks
• Summary

t.b.skaali_at_fys.uio.no http//www.fys.uio.no/elg/
alice
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Highlights

• ? Significant progress has been made the last 9
  months
• FEE general topology frozen
• Update and modification of mechanical structure
• System for individual APD bias control, equalizes
  gain factors, sucessfully tested
• Prototypes of i) new shaper card with low and
  high gain energy channels plus fast energy
  channel, and 2) ALTRO digitizer card, sucessfully
  tested August 2003
• Design of PHOS trigger card done, key elements
  now in lab test
• Back-end to DAQ use of TPC Readout Controller
  Unit, new RCU now in test
• ? However, only 16 months until operational
  system in first PHOS
• module, end 2004.

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Requirements and milestones

• Energy
• Dual gain energy channels and digitization for
  covering a very large dynamic range up to 100
  GeV
• Separate fast energy signal for trigger and
  timing
• Time-of-Flight
• Resolution 2 nsec to discriminate against low
  energy anti-neutrons
• Trigger
• L0 for min-bias pp, low threshold (?100 MeV)
• L1 for high pT Pb-Pb, high threshold (5-10 GeV)
• Milestones
• Electronic design Sep. 2003
• Production and installation in first PHOS module
  end 2004

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PHOS FEE as a black box
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FEE black box opened

• FEE board functionalities
• Shaper/amplifier slow dual gain outputs for
• energy, fast energy output for trigger
• Energy digitization
• Quadlet (2x2) analog summing of
• fast energy signals for PHOS trigger
• Timing (TBD)
• APD bias control other control channels

• Trigger/router board functionalities
• Data and Control GTL cable bus with FEEs and
  RCU
• Digitization of quadlets from FEE boards
• PHOS L0/L1 Trigger generation
• Router for event data stream via RCU to ALICE DAQ

• RCU Readout Controller Unit
• Main Controller, DDL to ALICE DAQ, DCS Ethernet

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FEE card geometry
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PHOS test August 2003
First test of PHOS ALTRO energy chain, cards
mounted on PHOS prototype
64 chs ALTRO card
New dual gain shaper, 3 cards 48 chs
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PHOS test August 2003
Beam data for a 3x3 crystal matrix, most of the
shower is deposited in the central crystal.
Sampling frequency 10 MHz.
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Timing channel

• Two methods
• TDC electronics for each channel
• Determining the time position of the sampled
  energy peak from a LSQ fit (the sampling clock is
  derived from the LHC clock).
• Simulations have been carried out by L. Musa,
  example to the right
• T sampling period ( 50 ns)
• ? pulse peaking time, 1 ?s, ratio T/ ?
  0.05
• N noise level in ADC bits
• ?t0 2.0E-3 x 1.0E-6 2 ns
• Doubling the peaking time will reduce ?t0
• Data from August 2003 run under analysis, may
  reach requirement with this method

Time and Amplitude resolution for N5LSB and T/t
from 0.05 to 1.
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PHOS trigger logic (simplified)

• Digitization of quadlet fast energy signals from
  shaper
• Sliding window algorithm implemented in FPGA
  for eight 28x16 crystal sub-matrices
• L0 decision after 600 ns, delivery at CTP in time
• Distance to ALICE Central Trigger Processor 38
  m, maximum latency at CTP 800 ns
• L1 decision
• Trigger level and algorithm fully programmable.
  Important also for EMCAL.
• Additional monitoring features
• Status first L0/L1 template simulated and
  synthesized
• Design H. Muller, R. Pimenta, EP/ED, see
  separate document

Trace I. Sibiriak, July 03
At 20 MHz sampling, max 3 samples over pulse
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PHOS trigger emulator

• Trigger emulator now in lab test
• Programmable amplifiers before digitization of
  fast quadlet signals from shaper board
• Digitization in ALTRO
• Emulator tested via PCI card

Card top (with ALTRO) and bottom
Courtesy H. Muller / R. Pimenta, CERN
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PHOS trigger logic
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Control channels on FEE board

• APD Bias Power System
• For equalization of channel gain
• Temperature probes
• Crystal volume, FEE boards
• Voltage monitoring
• Download of FPGA code
• Interfacing, see next page

Courtesy A. Vinogradov, Kurchatov
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Data control streams

• Event data stream FFE boards gt TRU gt RCU gt
  ALICE DDL gt ALICE DAQ
• Interface to ALICE Detector Control System via
  RCU Ethernet node
• All data and control traffic between FEE boards
  and TRU/RCU via GTL cable busses
• Monitoring data can be inserted into the event
  stream through a pseudo ALTRO in FPGA.
• However, most (all?) monitoring data will og to
  ALICE DCS data base

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From design to production

• Timeline
• Full prototype chain spring/summer 2004
• Testing and revison for production versions 3
  months
• Start production end summer 2004
• Design decisions
• Successful tests of FEE prototypes Summer 2003,
  leading up to
• gt Design meeting in Sarov, Russia, November 2003
• FEE modules
• APD preamp OK
• T-card OK
• FEE board basic prototypes tested, full
  integration design to be started ASAP. Time
  critical!
• Trigger/Router Unit design done, key elements in
  lab test
• RCU re-use TPC RCU, OK
• DCS channels APD control OK, must be integrated
  on FEE board. More work for other chs, plus
  integration design

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Summary and some conclusions

• Overall status
• very frontend (APD/preamp) and backend (TRU/RCU)
  on track!
• strong focus is needed on the FEE board design
  individual elements tested, but integration of
  low-noise analog electronics and high speed
  digital logic is not a piece of cake!
• Engineering tasks
• Designed as state-of-the-art electronics, the
  functionalities of the PHOS Front-End
  Electronics, Trigger and Readout chain, is
  implemented in programmable logic. A large effort
  is needed for FPGA programming, also after the
  system has been installed. In fact, the trigger
  logic will be further developed after the startup
  of ALICE.
• There is a lot of work in practical all areas, a
  critical issue is the organization and
  coordination of the project!