Trimaran A Few Notes

1
Trimaran A Few Notes

• For more see http//www.trimaran.org

2
Trimaran Installation System Requirements

• EECS account Best if you have one for this
  class
• See me if you dont have one
• We have 3 dual-core Linux machines for this class
• andrew, wilma, hugo feel free to use everyone
  will be given login access
• Other DCO machines should work too (if these get
  too busy or disks get full)
• DCO gets grumpy about using too much disk space
• If you want to use your own machine
• Linux
• Fedora Core 2-6 should work
• Other flavors of Unix should work, but no
  guarantees
• 1.5Gb disk space

3
Needed Software (older versions likely to work
but Im not certain)

• perl, gzip, gunzip
• gnu make 3.80
• autoconf 2.54, automake 1.7 (need these
  verions!)
• gcc we use 4.x, (3.4.4, 3.2 also should work)
• Gnu ranlib, ar (binutils 2.9 2.15)
• gdb 6.x, ddd 3.x
• tcsh Use this or you will have to translate
  some stuff
• emacs, vi, pico or whatever text editor you
  prefer
• Graph visualizing tools
• dot http//www.research.att.com/sw/tools/graphvi
  z
• TCL/TK v8.0p2 or higher (tclsh, wish)
• needed for Gui (I dont recommend you use gui)

4
Installation Step 1

• Source on the course webpage, trimaran.f07.tgz
• In your home directory, mkdir trimaran
• tar zxvf trimaran.f07.tgz
• Will create 6 subdirectories
• openimpact, elcor, simu, scripts, benchmarks, gui
• Enviroment variables/path this is critical!
• trimaran/scripts/envrc should have everything
  you need
• Or, trimaran/scripts/envrc.bash for you bash
  users
• Modify first line if you dont put trimaran in
  HOME/trimaran
• Add to your .cshrc, source trimaran/scripts/envrc
• So you dont forget

5
Installation Step 2

• Install impact
• cd trimaran/openimpact
• ./install_openimpact
• Fix errors that come up!
• May be a path problem i.e., executable its
  looking for is not in your path, so update your
  .cshrc/.bashrc
• Elcor install
• cd trimaran/elcor make
• Simu install
• cd trimaran/simu make

6
Trimaran Overview
C source
Frontend parsing, profiling function inlining,
memory dep analysis. Also, does some
backend stuff region formation, optimization
OpenImpact
Lcode HPL_PD specific Lcode, aka bridge code
Elcor
Backend analysis, optimization,
scheduling register allocation, code generation
Rebel
Simu
Emulator emulate VLIW semantics using C code
compiled simulation
C emulation code
7
Running Trimaran

• Install trimaran, verify your code works on
  strcpy and wc
• Trimaran-gui I dont like/use this
• tcc gcc equivalent, sorta!
• Command line way to invoke entire system Gui
  calls this
• tcc help to get options
• tcc bench strcpy to run strcpy with basic
  blocks
• Save output to examine
• trimaran/benchmarks
• source, compile flags, link flags
• input for profiling the code, output to check if
  ran properly
• To add a new benchmark, follow the organization
  that is there

8
Elcor The Basics

• EL COmpiler Real (use spanish accent, real ray
  al)
• El camino real famous road in Silicon valley
• Rebel REgion-Based Elcor Language
• Textual IR for the compiler
• Elcor operates as a Rebel ? Rebel converter
• Rebel ? do some transform ? Rebel
• Second choice was Beavis (Basic Elcor Advanced
  VISualization language) But the name just did
  not take off ?
• Basic control flow graph and assembly listing
• Lcode/tr code Low-level code (Impact)
• HPL_PD specific Lcode is the input to elcor
  (O_tr files)
• elcor can read either Lcode or Rebel and output
  either

9
Running Elcor Manually

• Compiling a benchmark
• tcc bench strcpy
• strcpy_O directory created
• impact_intermediate
• elcor_intermediate
• strcpy.O_tr.tgz impact output / elcor input
  (bridge code)
• Impact assembly (called Lcode or Mcode)
• This is what you will run Elcor manually on
• Untar this file
• file1.O_tr, file2.O_tr,
• 1 file per original C source file
• strcpy.O_el.tgz elcor output
• Rebel
• host_layout_info.md data structure organization
  stuff
• simu_intermediate

10
Running Elcor Manually (2)

• Convert Lcode to Rebel
• Get used to Rebel no need to worry about 2
  assembly codes
• elcor i strcpy.O_tr o strcpy.O_reb
  Foutput_formatrebel \Fdo_null_processingyes
• strcpy.O_reb is our input file
• Run elcor
• Default input/output format is Lcode (see
  IO_DEFAULTS)
• elcor i strcpy.O_reb o strcpy.O_el
  Finput_formatrebel \Foutput_formatrebel
• Can also just directly use the strcpy.O_tr file
  if you wish
• After, perform scheduling (may want to disable
  this during debugging, see elcor/parms/DRIVER_DEFA
  ULTS)

11
Running Simu Manually

• simu
• Converts Rebel to C
• Models VLIW architecture properly
• predicates, NUAL, etc.
• Allows testing the compiler is correct!
• running simu (aka codegen)
• codegen el strcpy.O_el o strcpy.c
  Finput_formatrebel \Femulate_unscheduledyes/n
  o Femulate_virtual_regsyes/no
• strcpy.c
• benchmark_data_init.simu.c
• Note need host_layout_info.md in the directory
• gcc m32 malign-double IHOME/trimaran/simu/src/
  emulib \LHOME/trimaran/simu/lib .c lequals
  lm
• ./a.out gt output, diff output verses expected
  output

12
Elcor Organization

• src/Tools
• homegrown version of STL - list, dlist, slist,
  hash_set, hash_map,
• src/Graph
• All the core compiler data structs in here
• operand.h, port.h, op.h, region.h, edge.h,
  _utilities.h, opcode_properties.h
• Main
• process_function.cpp is the main driver
• Mdes
• target processor info built from .lmdes2 file
• Analysis
• control flow, dataflow analysis, predicate
  analysis, edge drawing
• Control
• Control flow transformations
• Templates
• Whenever you create a Listltfoogt that has never
  been done before
• Must instantiate template look in the files for
  example
• Hw1 add to eecs583/templates.cpp

13
Core IR (See elcor/src/Graph)

• Primary data structures
• Region (region.h)
• Procedure, Basicblock, Hyperblock, LoopBody
• Op (op.h)
• id, opcode, dests, srcs, pred
• Operand (operand.h)
• Register, Macro_reg, Literal each has data type
• Opcode (opcode.h)
• Giant enum!
• Data type (dtype.h)
• Flt/int, signed/unsigned, width
• Edge (edge.h)
• Register, memory, control depencences Base IR
  only has C0 edges, other edges created for
  scheduling via edge drawing

14
Core IR (continued)

• Defn control edges
• C0 control flow (always around, even sequential
  flow)
• C1 control dependence (not in by default)
• Operation-level control flow graph
• All ops connected to/from with C0 edges
• Branches have multiple outgoing C0 edges
• Regions are layered on top
• Regions must be perfectly nested
• Basicblocks, Hyperblocks, and Procedures are all
  you need to worry about now.
• All basicblock/hyperblocks start with C_MERGE and
  end with a branch (if no branch, then DUMMY_BR
  used)

15
Use of Iterators

• Primary way to traverse the IR
• All Tools have iterators
• List_iterator, Hash_set_iterator, etc.
• IR also has iterators, see src/Graph/iterators.cp
  p,h
• Region_entry_edges/ops
• Go through entry edges/ops note only control
  flow edges
• Also exit versions of these
• Region_ops_C0_order sequential walk of ops
• Region_subregions nested regions in layout
  order
• Op_explicit_sources or dests
• Note variants of these sources vs inputs,
  explicit vs implicit