Latest In Depth Measurements on Front End Boards FEBs Used in the Vertical Slice Test VST

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Latest In Depth Measurements on Front End Boards
(FEBs) Used in the Vertical Slice Test (VST)

• Jesse Chvojka
• Jennifer Seger
• February 22nd, 2006
• University of Rochester

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In Depth Measurements

• In Depth Test
• ?Trip Chip Gain bit setting of 11 (this is the
  setting we use in the VST)
• ?Look at one channel on each board at a variety
  of charge injection amounts
• ?variety relevant charge amount (multiples of
  80 fC)

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Board 5 Gain Bit Setting of 11, Ch 0
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Board 6 Gain Bit Setting of 11, Ch 0
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Board 7 Gain Bit Setting of 11, Ch 0
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Board 8 Gain Bit Setting of 11, Ch 0
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Conclusions

• ?Boards are roughly linear
• ?Gain is a little higher than we anticipated, we
  expected about 0.5 adc counts per fC for high
  gain