FLEXBUS: A HighPerformance SystemonChip Communication Architecture with a Dynamically Configurable T

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FLEXBUS A High-Performance System-on-Chip
Communication Architecture with a Dynamically
Configurable Topology

• Krishna Sekar, Kanishka Lahiri, Anand
  Raghunathan, Sujit Dey

Mobile Embedded Systems Design Test
Lab, Dept. of ECE, Univ. of California, San Diego
NEC Laboratories America, Princeton, NJ
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On-Chip Communication in System-on-Chip Designs

• Increasing complexity
• Increasing traffic volume diversity
• Decreasing efficiency of global wires

On-chip communication significant limiter for
system performance
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Configurable Bus-Based Communication Architectures

• Static (design time) configurability
• Available in many state of the art buses (AMBA,
  Sonics)
• Topology (e.g., number of buses, bus widths)
• Protocol (e.g., arbitration algorithm)
• Mapping (components to buses)

• Dynamic Configurability
• Enables adapting to run-time variation in traffic
  characteristics
• Many buses (e.g. AMBA) allow run-time tuning of
  protocol parameters such as bus priorities)
• We propose dynamic topology configurability
• Dynamic bridge by-pass
• Dynamic component re-mapping

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Dynamic Topology Configurability Motivation
M1
M2
M3
M4
Bus1
Bus2
S1
S2
Bridge

• Advantages/disadvantages of bridge-based buses
• Reduce bus conflicts during concurrent
  operation
• Enable high frequency operation of each segment
• Interface sub-systems with different clock
  frequencies

• Large latency and throughput penalty for
  communication across bridges
• 5X throughput reduction in the case of AHB-AHB
  bridge

• Dynamic Topology Configurability Goals
• Provision for run-time configuration of
  component-bus connectivity
• Minimize hardware overhead
• Compatibility with legacy components

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Dynamic Bridge By-pass Architecture
select_S1
grant_M2
busreq_M3
Arbiter1
busreq_M2
Arbiter2
grant_M3
busreqBRG
Decoder1
grant_M1
Decoder2
grantBRG
selectBRG
select_S2
busreq_M1
Slave2
Master1
BRGSlvI/F
BRGMstI/F
Master2
Master3
Slave1
Bridge
AHB1
AHB2

• Worst case reconfiguration overhead 17 cycles

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Dynamic Component Re-mapping Architecture
Master2
busreq_M2
grant_M2
busreq_BRG
grant_M1
Arbiter2
busreq_BRG
Arbiter1
busreq_M1
grant_BRG
grant_BRG
MstI/F
MstI/F
Slave2
Master1
SlvI/F
SlvI/F
BRG
Decoder1
Decoder2
select_S3
selectBRG
selectBRG
AHB2
AHB1
select_S2
Slave1
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Dynamic Configuration Policy

• History-based heuristic
• For two segment bus, over time period TP observe
• NBus1 No. of transactions on BUS1
• NBus2 No. of transactions on BUS2
• NBrg No. of transactions across BRIDGE
• TSingle Time under single bus mode
  (NBus1NBus2NBrg) ? Cycleslocal ?
  clkPeriodSingle
• TMultiple Time under multiple bus mode
  max(NBus1,NBus2) ? Cycleslocal ?
  clkPeriodMultiple NBrg ? CyclesBrg
  ? clkPeriodMultiple
• If TSingle lt TMultiple , choose single bus, else
  multiple bus
• Time period TP adaptive
• Trade-off between responsiveness to traffic
  variations andreconfiguration overhead

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Hardware Implementation Results

• FLEXBUS implemented on top of Synopsys DesignWare
  AMBA IP
• Synthesis, floorplanning and timing analysis
  under different bus architectures for NEC 0.13 µm
  technology

Bus Architecture
Chip Area(sq. mm)
Frequency(MHz)
Delay(ns)
Single Shared Bus
82.12
218
4.59
Multiple Bus
84.27
264
3.79
FLEXBUS (single bus mode)
212
82.66
4.72
FLEXBUS (multiple bus mode)
254
3.93

• FLEXBUS incurs
• Negligible area overhead
• 3.2 average delay penalty

System Floorplan under FLEXBUS
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Case Study 802.11 MAC processor
WEP
FCS
ARM946ES
AMBA AHB
Key Buffer
LLC
PLI
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Performance under Random Traffic

• Traffic generated using two-state Markov model
• Varying granularity of local and cross-bridge
  transactions

• FLEXBUS configurations selected by Dynamic
  Configuration Policy

• FLEXBUS performance improvements
• 21.3 over single shared bus
• 17.5 over multiple bus

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Conclusions and Future Work

• Importance of topology configurability in on-chip
  communication architectures
• FLEXBUS novel bus architecture with dynamically
  configurable topology
• Dynamic bridge by-pass
• Dynamic component re-mapping
• Significant performance benefits compared to
  static bus architectures

• Future Work
• Extend FLEXBUS to more complex communication
  architectures

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Background Bus-based Communication Architectures
busreq2
select2
Arbiter
Address Decoder
grant2
busreq1
select1
grant1
address, control, wdata1
Master1
Slave1
address, control, wdata2
ready1, response1, rdata1
Master2
Slave2
ready2, response2, rdata2
AMBA AHB Bus Architecture
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Experimental Setup
Vera Master BFM
Vera Master BFM
read ( ) idle ( )
read ( ) idle ( )
DesignWare AMBA AHB
Vera Slave BFM
Vera Slave BFM

• Synopsys DesignWare reference AMBA implementation
• AHB blocks
• Bus Bridge
• Reconfigurable bus designed by modifying Synopsys
  AMBA implementation
• Vera models for bus masters and slaves
• Can model bus transactions using read(),
  write(),idle() etc calls

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Presentation Overview

• On-chip communication architectures Introduction
• Dynamic topology configurability in bus-based
  architectures
• FLEXBUS architecture
• Design Innovations Bridge Bypass, Component
  re-mapping
• Run-time configuration policies
• Experimental results
• Conclusions