Lecture 2b: SRAM

1
Lecture 2bSRAM

• SFSU ENGR 852
• Spring 2003
• 2/17

2
Resources

• http//fizbin.eecs.lehigh.edu/mschulte/ece319/CH9
  _Slides.pdf

3
SRAM Review

• Circuit
• To WRITE
• CEWE0, OE1, ADDRESS, DATA
• To READ
• CEOE0, WE1, ADDRESS

4
SRAM Review

• READ Dangers
• Trying to OUTPUT(READ) and grab data on same
  clock edge
• Turning off READ on same edge as grabbing data
• WRITE Dangers
• WRITEing while address is changing
• Turning off RAM while WRITEing

5
SRAM Review

• READ system

6
SRAM Review

• READ Dangers
• Trying to OUTPUT(READ) and grab data on same
  clock edge

Addr Data
CE
7
SRAM Review

• Flip-flop Timing
• Setup Time Time before clock edge that the value
  of the data must not change
• Hold Time Time after clock edge that value of
  data must not change

8
SRAM Review

• Flip-Flop Timing Violations

Setup Time
Hold Time
Data transitions can be caused by a change in
address or enabling the RAM (OE).
9
SRAM Review

• Flip-Flop Timing Violations

Setup Time
Hold Time
Data
Data transitions can be caused by a change in
address or enabling the RAM (OE).
10
SRAM Review

• READ Dangers
• Turning off READ on same edge as grabbing data

OE
FF ENABLE
Addr Data
CE
11
SRAM Review

• READ Dangers
• Only way to get a setup time violation

OE
Setup time
FF ENABLE
Addr Data
CE
12
SRAM Review

• WRITE Dangers
• WRITEing while address is changing

CLK
WE
1000 1010 1011 1111 0111
Addr Data
OE
CE
13
SRAM Review

• WRITE Dangers
• Turning off RAM while WRITEing

OE
FF ENABLE
Addr Data
CE
14
SRAM Review

• WRITE Dangers
• Turning off RAM while WRITEing

FF ENABLE
Addr Data
CE