IEEE 1588 Hardware for Fault Tolerance and High Precision

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IEEE 1588 Hardware for Fault Tolerance and High
Precision

• Patrick Loschmidt
• Georg Gaderer
• Nikolaus Kerö

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Rationale

• Flexible hardware platform to accommodate
• TC - Transparent Clock capabilities
• High accuracy time stamping
• Fault tolerant clock synchronization
• Constraints and requirements
• On-the-fly time stamping
• Yet maintaining full switch functionality for 8
  ports
• Port based VLAN
• Trunking
• QoS

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IEEE1588 Standard

• Master-Slave based
• Not restricted to a particular network technology
• Strategy
• Delay-Request and Delay-Response packets
• Synchronization packets
• Network delay is considered
• Problem master failure results in a new master
  election

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Democratic Approaches - Syn1588

• Democratic approach
• No dedicated master
• No master selection
• Every node spreads its local time to every other
  node
• On-the-fly time stamping
• Failure of F in 2F1 nodes can be detected
• Underlying Principles
• Interval-based paradigm
• Adder-based clock (ABC)
• Local time is a continuous function of real time

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Problem Definition for Ethernet-IEEE1588

• Single point of failure Master
• Master fault causes a new master election
• Babbling idiot problem
• Master election
• Up to 10 sync periods
• Efficiency master-slave vs. democratic (of
  links)
• n number of nodes
• ?Efficiency decreases with of nodes

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Master Group Concept

• Master Group
• Syn1588 group
• Fault tolerant (backup nodes)
• Some nodes with GPS
• IEEE1588 Slaves
• Time sync standard compliant
• Less traffic between Master Group speaker and
  slaves
• New efficiency with m masters
• usual case mn

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Fault Tolerant Switch

• Ethernet Switch is single point of failure
• Fault tolerant switch concept, with special
  respect to clock synchronization
• Hardware considerations
• Multiple clocks within one chip
• Doubling of hardware (including power supply)
• Hot standby unit as backup
• Full fault tolerance with at least 3 units
• Voting within IC
• Several independent modules

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Scalability

• Synchronization between master groups
• Backup speaker if group/speaker fails
• Inter-switch communication needed
• Speaker-switch is transparent for nodes

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Syn1588 Transparent Switch Version 1
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Design Considerations

• 3rd party switch to obtain full switch
  functionality
• 8 MII ports without physicals
• Fully manageable
• No external devices required (Memory, boot
  device)
• Zarlink family was chosen
• Complex FPGA to handle all Syn1588 stuff
• External CPU attachable via standard interface
• Limited hardware design effort
• Linux support and reduced software efforts
• 3rd party module (X-Board)

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Basic Block Diagram
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Functional Block Diagram
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Detailed Block Diagram
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Accuracy Issues I

• Time stamp resolution
• High resolution clocks (96 bits)
• High speed logic for time stamping
• Accuracy
• Stable oscillator to be used for local clock of
  switch
• MII Interface vs RMII Interface
• Pin count
• Complexity
• EMC Issues vs. accuracy

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Accuracy Issues II

• PHY provides clocks for sending and receiving
  data
• PLL locks to sender clock domain (hopefully)
• Minimal phase jitter only introduced once in TS
  unit

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Accuracy Issues III

• One common 50 MHz Reference Clock
• Additional phase jitter introduced between sender
  and TS unit
• One consolidation layer more in RX Direction
• TX timestamp is not added at phase locked point

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Accuracy Issues IV

• Independent TCs

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Accuracy Issues V

• Sampling unit operates at 400 MHz
• 2.5 ns mean inaccuracy
• Residual chip operates at 100 MHz

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Syn1588 -Switch, a First Glance
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• Questions?

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Syn1588 Adder Based Clock Structure
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Syn1588 Adder Based Clock 2

• IEEE 1588 Adder Based Clock Register Layout