Make a BPM out of a Damper

1
Make a BPM out of a Damper?
2
Digital Damper
53 MHz, TCLK, MDAT,...
106 / 212 MHz
Stripline Pickup
FAST ADC
Monster FPGA(s)
Minimal Analog Filter
14
Transverse Dampers Identical X Y
FAST ADC
Minimal Analog Filter
Stripline Kicker
Power Amp
Ethernet
FAST DACs
2-10
gt 27 MHz
Resistive Wall Monitor
FAST ADC
Minimal Analog Filter
Longi- tudinal (Z) Damper
Broadband Cavity
Power Amp
FAST DACs
2-10
3
Damper -gt BPM
Stripline Pickup
FAST ADC
Analog Filter
M E M O R Y
12
FAST ADC
Analog Filter
BPMs H V
VME
Stripline Pickup
FPGA
FAST ADC
Analog Filter
12
FAST ADC
Analog Filter
Delay line per ADC
FPGA
212 MHz
Timing Logic
53 MHz, TCLK, MDAT,...
4
BPM Pick-ups
V M E
FADC 4 Chan/2 BPM
Sample Timing
UCD
Clocks and Timing
VME CPU EDB PMC
ACNET
BLM
5
BPM Pick-ups
V M E
FADC 4 Chan/2 BPM
Timing and EDB/BLM
BLM
Clocks and Timing
VME CPU
ACNET
6
So What Do We Get?

• Minimum A Sample every bucket, allowing
  filtering and averaging everything with
  everything. Multiple data streams.
• Synchronous sampling and phasing can be beam
  triggered.
• Sampling based on the beam structure, i.e the
  FPGA data rate is proportional to the beam
  structure.
• We can time-separate the proton signal from the
  antiProton signal.

7
FPGA Logic example
Memory Interface
Analog Scope
Out-of-bunch Data
Memory Interface
Threshold
Anti-Gate
212MHz Samples
Memory Interface
Turn Average
Gate
Memory
Memory Interface
Bunch n TbyT Filter
Bunch Structure Timing
Memory Interface
Bunch m TbyT Filter
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What is the bad news?

• It isn't a perfect fit to our problem but the
  core design is close enough that we should be
  able to use it.
• It isn't a production board just a good core
  design we can build upon.
• It is complete over-kill but it costs 400-500
  per channel today, quantity one.

9
What needs to be done?

• Determine the Analog Filter to use
• Nothing??
• Low Pass Filter only?
• Switchable Bandpass Filter to spread the pulse
  width on uncoalesed bunches?
• Determine functionality of current board and
  stuff another one for our testing.
• Soon, channel decision. Then layout new board
  and simulation of VHDL logic.

10
Webber Questions

• are there parallel, simultaneous position
  processing issues in the new requirements that
  the FDB architecture can/cannot satisfy?
• Nope
• what are the requirements for switching between
  modes in a short time?
• Run several modes in parallel
• is the FDB pipeline/FIFO processing
  architecture limiting in any significant way
  relative to TeV requirements?
• No FIFO, FPGA pipeline runs faster than data
  rate.
• are implied VME backplane data rates
  acceptable?
• VME rates are ACNET request dependent. Boards can
  buffer data.
• what might be possibility of excessive loading
  on VME CPU?
• Programmer dependent.
• what are the triggering implications and
  requirements on external timing/triggering
  system?
• Noticeable, timing must sync to accelerator clock.