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2141310 Micro and Nanofabrication Technology


... lengths much smaller than a micrometer is a challenge, and the difficulties ... Microlithography refers to features in the order of 10 micrometers or less. ... – PowerPoint PPT presentation

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Title: 2141310 Micro and Nanofabrication Technology

2141310 Micro and Nanofabrication Technology
  • Dr. Waleed S. Mohammed
  • Postdoctoral fellow at ECE, University of
    Toronto, Canada, (2004-2007)
  • Ph.D. College of optics and photonic, University
    of Central Florida, USA (2004)
  • M.Sc. College of optics and photonic, University
    of Central Florida, USA (2001)
  • M.Sc. Computer Engineering, Cairo University,
    Egypt (1999)
  • B.Sc. Electrical and electronic engineering,
    Cairo University, Egypt (1996)

Lect1 Background
  • Micro/Nano fabrication is important for several
    fields of interest
  • - Electronics integrated circuits-Radiometry
    and detection
  • micro-antennas arrays
  • - Photonics micro lenses, photonic crystals,
    Quantum dots gratings.- Electro-mechanics
  • MEMS (Micro electro-mechanical structures).
  • -Artificial materials
  • Nano-crystals, nano-tubes.
  • Here we will focus on integrated

  • Micro Technology A technology which focuses on
    miniaturizing bulk component to dimensions in
    the order of micron and sub-micron, while keeping
    their functionality.The extremely small devices
    are fabricated on wafers.Wafers are thin layers
    of a substrate material, usually semiconductor or
  • Important factors1- Compactness The size of the
    components.2- Capacity The number of components
    produced on one wafer.3- Integration Building
    the whole circuit on one chip.4- Functionality
    The performance of the device built on one wafer.
  • Component size depends on the technology.
  • Reducing the components size increases the
    capacity exponentially.
  • Increasing the capacity allows building more
    circuits with different components on one wafer.
  • Integrating more circuits on one chip increases
    its functionality.

Background Wafer size and capacity
  • Wafers come in different diameters4,6,8,12,14
    , and 16
  • The surface of the wafer is divided into square
    dice (10-mmx10-mm).
  • Each integrated circuit is fabricated in one die.
  • The total capacity of the wafer is
    where N is the total
    number of components, D is the wafer diameter, d
    is die
    dimension and Ndie is the number of components
    per die.

Background compactness and capacity
  • The first successful fabrication techniques
    produced single transistor on a rectangular
    silicon die 1-2 mm.
  • The first integrated circuits included several
    transistors and resistors. (1960)
  • The level of integration doubles every one or
    two years. (Moores law)
  • Compared to the first mm size transistor, now
    billions of transistors are produced in
    20-mmx20-mm chips.

Background The technology
  • The bulk component are miniaturized on wafers.
    Then, we need to grow the wafers of the material
    of interest (i.e. Crystalline Silicon).
  • Realizing diodes, resistors, capacitors and
    connectors on semiconductor wafers requires
    extra layers of metals, insulators and
    semiconductors.Then, we need to deposit these
    layers on the wafer.
  • Each component has a different layout and they
    need to be connected.Then, we need to generate
    and realize certain patterns on the wafer andthe
    deposited layers.
  • Finally, we need to test the devices.

  • A traditional metaloxidesemiconductor (MOS) is
    obtained by depositing a layer of Silicon
    dioxide (SiO2) and a layer of metal
    (polycrystalline Silicon) is actually used
    instead of metal) on top of a semiconductor die.
  • As the silicon dioxide is a dielectric material
    its structure is equivalent to a plane
    capacitor, with one of the electrodes replaced
    by a semiconductor.
  • When a voltage is applied across a MOS
    structure, it modifies the distribution of
    charges in the semiconductor.
  • Considering P-type semiconductor, a positive VGB
    tends to reduce the concentration of holes and
    increase the concentration of electrons.
  • If VGB is high enough, the concentration of
    negative charge carriers near the gate is more
    than that of positive charges, in what is known
    as an inversion layer.
  • This structure with P-type body is the basis of
    the N-type MOSFET, which requires the addition of
    an N-type source and drain regions.

  • A metaloxidesemiconductor field-effect
    transistor (MOSFET) is based on the modulation of
    charge concentration caused by a MOS capacitance.
  • It includes two terminals (source and drain) each
    connected to separate highly doped regions of the
    same type (either P or N type)
  • These source and drain are separated by a doped
    region of opposite type, known as the body.
  • The body is not highly doped.
  • The active region constitutes a MOS capacitance
    with a third electrode, the gate, which is
    located above the body and insulated from all of
    the other regions by an oxide layer.

The plus sign () in the figure near the N
means heavy doping. The lack of the sign near P
represents un-doped region.
  • nMOS FET when the MOSFET is an N-Channel, then
    the source and drain are 'N' regions and the
    body is a 'P' region.
  • When a positive gate-source voltage is applied,
    it creates an N-channel at the surface of the P
    region, just under the oxide, by depleting this
    region of holes.
  • This channel extends between the source and the
    drain, but current is conducted through it only
    when the gate potential is high enough to attract
    electrons from the source into the channel.
  • When zero or negative voltage is applied between
    gate and source, the channel disappears and no
    current can flow between the source and the drain.

MOSFET Modes of operation
  • Cut-off or sub-threshold mode
  • When VGS lt Vth where Vth is the threshold voltage
    of the device.
  • The transistor is turned off, and there is no
    conduction between drain and source.
  • Triode or linear region
  • When VGS gt Vth and VDS lt (VGS - Vth)
  • The transistor is turned on, and a channel
  • has been created which allows current to
  • flow between the drain and source. The MOSFET
    operates like a resistor, controlled
  • by the gate voltage relative to both the source
  • where µn is the charge-carrier effective
    mobility, W is the gate width, L is the gate
  • length and Cox is the gate oxide capacitance per
    unit area.

MOSFET Modes of operation
  • Saturation
  • When VGS gt Vth and VDS gt VGS - Vth
  • The switch is turned on, and a channel has been
    created, which allows current to flow between
    the drain and source.
  • Since the drain voltage is higher than the gate
    voltage, a portion of the channel is turned off.
    The onset of this region is also known as
    pinch-off. The drain current is now relatively
    independent of the drain voltage (in a
    first-order approximation) and the current is
    controlled by only the gatesource voltage,
    modeled as

MOSFET Modes of operation
MOSFET Scaling
  • MOSFET scaling
  • Over the past decades, the MOSFET has
    continually been scaled down in size typical
    MOSFET channel lengths were once several
    micrometers, but modern integrated circuits are
    incorporating MOSFETs with channel lengths of
    less than a tenth of a micrometer.
  • Reasons for MOSFET scaling 1- Smaller MOSFETs
    may allow more current to pass, due to their
    shorter length dimension conceptually,
    MOSFETs are like resistors in the on-state, and
    shorter resistors have less
    resistance 2- Smaller MOSFETs have smaller
    gate areas, and thus lower gate capacitance. 3-
    Reduced area leads to reduced cost.
  • These first two factors contribute to lower
    switching times, and thus higher processing
    speeds, and lower energy per switching event.
    Smaller MOSFETs can be packed more densely,
    resulting in either smaller chips or chips with
    more computing power in the same area. Since
    fabrication costs for a semiconductor wafer are
    relatively fixed, the cost per integrated
    circuits is mainly related to the number of chips
    that can be produced per wafer. Hence, smaller
    ICs allow more chips per wafer, reducing the
    price per chip.
  • Difficulties arising due to MOSFET scaling
  • Producing MOSFETs with channel lengths much
    smaller than a micrometer is a challenge, and the
    difficulties of semiconductor device fabrication
    are always a limiting factor in advancing
    integrated circuit technology. In recent years,
    the small size of the MOSFET, below a few tenths
    of a micrometer, has created operational problems.

MOSFET Processes
  • The wafer is made out of extremely pure silicon
    that is grown into mono-crystalline cylinders
    using the Czochralski process.
  • MOS structure is fabricated through the repeated
    application of a number of process

MOSFET Processes
  • Silicon oxidization is a way to produce a thin
    layer of oxide (usually silicon dioxide) on the
    wafer by heating the silicon in high temperatures
    in the presence of Oxygen.
  • Chemical vapor deposition (CVD) is a chemical
    process used to produce high-purity,
    high-performance thin films of solid materials
    (silicone nitride, silicon dioxide, polysilicon
    and metals) out of a gaseous mixture onto the
    surface of the wafer.
  • Sputtering is a physical vapor deposition (PVD)
    process whereby atoms in a solid target material
    are ejected into the gas phase due to bombardment
    of the material by energetic ions. It is commonly
    used for thin-film deposition of metals ad
  • Diffusion is a process where thin layer of
    n-type or p-type are formed by high temperature
    diffusion of donors or acceptors impurities into
  • Ion implantation is a process by which ions of a
    material (donors or acceptors) can be implanted
    into another solid, thereby changing the physical
    properties of the solid.
  • Spin coating is a procedure used to apply uniform
    thin films to flat substrates by rotating an
    excess amount of the solvent placed on the
    substrate at high speed in order to spread the
    fluid by centrifugal force.

MOSFET Processes
  • Epitaxy The term epitaxy (Greek epi "above" and
    taxis "in ordered manner") describes an ordered
    crystalline growth on a monocrystalline substrate
    Epitaxial films may be grown from -
    gaseous precursors (Vapor-phase epitaxy, VPE)
    - or liquid precursors (Liquid-phase
    epitaxy, LPE).
  • Annealing It is a process that produces
    conditions by heating and maintaining at a
    suitable temperature, and then cooling very
    slowly. It is used to induce softness, relieve
    internal stresses, refine the structure and
    improve cold working properties.
  • lithography Microlithography and nanolithography
    refer to pattern generating methods capable of
    structuring material on a fine scale.
    Microlithography refers to features in the order
    of 10 micrometers or less.Nanolithography refers
    to features in the order of 100 nanometers or
    less. - Photolithography, which uses photons
    to generate patterns on
    photosensetive materials (phot-resists).
    - Electron-beam (ebeam) lithography,
    which uses electrons to create patterns
    on ebeam-resists.
  • Etching is a process of transferring the
    lithographic generated patterns into the desired
    substrate material.

Lect. 3 MOSFET Processes
P-type silicon substrate
  • Thin layer of SiO2 is formed by oxidization.
  • A Silicone Nitride layer is deposited on the
    surface using chemical-vapor deposition (CVD) as
    a protection layer.
  • A layer of photo-resist is spun for the
    photo-lithography step.

P-type silicon substrate
Silicon Nitride
P-type silicon substrate
Spin coating
P-type silicon substrate
MOSFET Processes
  • Using photo-lithography, the resist is removed
    except from the region where the MOS structure
    will be formed.
  • The silicon nitride and silicon dioxide layers
    are etched down
  • Using ion-implantation, the n-type source and
    drain regions are formed.

P-type silicon substrate
P-type silicon substrate
Ion implantation
P-type silicon substrate
MOSFET Processes
  • The protection layers of SiO2 and silicon nitride
    are etched down.
  • The silicon nitride and silicon dioxide layers
    are etched down
  • Using ion-implantation, the n-type source and
    drain regions are formed.

P-type silicon substrate
P-type silicon substrate
P-type silicon substrate
MOSFET Processes
  • The protection layers of SiO2 and silicon nitride
    are etched down.
  • The silicon nitride and silicon dioxide layers
    are etched down
  • A layer of SiO2 is deposited using CVD and a
    photo-resist is spun coated on top of it for the
    lithography process.

Spin-coating photolithography
P-type silicon substrate
P-type silicon substrate
P-type silicon substrate
MOSFET Processes
  • The SiO2 mask is etched to open for the ohmic
    connectors to the source and drain.
  • A layer of metal is sputtered then a
    photo-lithography and etching steps are followed
    to remove the metal except from the desired
    locations. .

P-type silicon substrate
Sputtering spin-coating Photolithography Etchi
P-type silicon substrate
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