FMD: Silicon multiplicity detectors

1
FMD Silicon multiplicity detectors
Thermal simulation meeting, CERN, 11 November
2002 Børge Svane Nielsen Niels Bohr Institute

1. Geometry of FMD, T0 and V0 detectors
2. Material constants for FMD
3. Heat dissipation of FMD

2
FWD detectors layout
3
Si1, T0_r V0_r layout
4
Si2 layout
5
Si3, T0_l V0_l layout
6
CERN maquette 11
ITS-pixels
V0-R
T0-R
Si1 (inner)
Si1(outer)
Absorber
7
FMD ring layout
Full FMD 3 inner rings 2 outer rings
Inner Rin4.2 cm Rout17.2 cm Outer Rin15.4
cm Rout28.4 cm
128
256
20x2x1285120 10x2x2565120
8
Si1 assembly
Si detectors
Read-out electronics card on support plate back
side
Support plates
9
Hybrid with Viking chips
Connector(s) for power, control, read-out

• Hybrid cards contain
• FE chips
• Bias voltages distribution
• Gate/strobe distribution
• Read-out clock distribution
• Detector bias connection

Other components

• Read-out cards contain
• Bias voltages generation
• Gate/strobe distribution
• Read-out clock generation
• Remote connections

VA preampshaper 128 ch
Si detector
10
FMD Material constants
Material type and thickness of one Si detector
ring
Layer Material Thickness Heat conductivity (W/mK) Density (kg/m3) Specific heat (J/kg?K)
Silicon detector Si 0.3 mm 84 2330 678
Hybrid Al2O3 0.5 mm 35 3970 880
FE electronics air chips 10 mm (mostly air)
Support Carbon fibre or aluminium honeycomb 2?0.5 mm C or Al 10 mm air C 24 Al 222 C 2200 Al 2700 C 691 Al 900
11
FMD Material constants
Material type and thickness of one Si detector
ring
Layer Material Thickness Interaction length Radiation length
Silicon detector Si 0.3 mm 0.6 10-3 0.3 10-2
Hybrid Al2O3 0.5 mm 2.0 10-3 1.0 10-2
FE electronics air chips 10 mm (mostly air)
Support Carbon fibre or aluminium honeycomb 2?0.5 mm C or Al 10 mm air C 2.6 10-3 Al 2.5 10-3 C 0.5 10-2 Al 1.1 10-2
Total thickness of one Si ring C
5.2 10-3 ?I 1.8 10-2 X0

Al 5.1 10-3 ?I 2.4
10-2 X0
12
FMD electronics
FMD channel count
Segments (wafers) Phi sectors Radial sectors Hybrids Chips/ hybrid FE chips FE channels
Si1 inner 10 20 (256) 512 10 (16) 8 (160) 80 (5,120) 10,240
Si1 outer 20 40 (128) 256 20 (8) 4 (160) 80 (5,120) 10,240
Si2 inner 10 20 (256) 512 10 (16) 8 (160) 80 (5,120) 10,240
Si2 outer 20 40 (128) 256 20 (8) 4 (160) 80 (5,120) 10,240
Si3 10 20 (256) 512 10 (16) 8 (160) 80 (5,120) 10,240
Total system 70 140 70 (720) 360 (25,600) 51,200
Note We are looking into increasing the number
of strips, but use more integrated FE
chips - red values. In the following, I assume
the new numbers.
13
Heat dissipation
Heat dissipated by FE electronics of one Si
detector ring
VA1TA preamp chip (128 channels) 150 mW
? 80 chips 12 W / ring For
simulation assume uniform distribution on
hybrid surface (towards
support plate) Read-out electronics and power
distribution ? 5 W / ring For simulation
assume concentrated in 2 locations near outer
radius