Cluster Processor Module

1
Cluster Processor Module

• Status, Test plans and Timescale

2
Status

• 47 sheets
• Modifications since Bham joint meeting
• splitting of packages Hit merger, ROC RoI and
  DATA
• I2C access
• Definition of a format for the ROD

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47 Sheets

• Not easy to browse through
• 3 times the GTM

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Splitting of Packages

• Reduce some track lengths
• Same package for different blocks
• Reduce the cost
• Blocks concerned

5
Choice of packages
-gt Design nearly finished some VME registers and
testpoints to add, could be done later.
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TTCrx access I2C controller

• TTCrx access is done by only setting 2 VME
  registers
• data
• select address
• Logical device has been implemented to access the
  I2C bus

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Glink to ROD data

• ROD DATA Format

G link port
SRL
8 TT
WH
12 bits BCN
HH
Th 16
48 bits HIT results
BE
AE
Th 2
Th 1
VE
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Glink to ROD RoI

• ROD RoI Format

Glink port
Not use
CP chips
R
H
L
12 bit BCN
B
A
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Information available on the Web

• Backplane schematic
• VME memory map
• Schematic in PDF format soon
• http//www.ep.ph/bham.ac.uk/user/staley

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Test plans

• Check supply
• Boundary scan
• FPGA Xilinx Xchecker
• CPLD Altera Byteblaster
• Crate depend timescale, board could be ready as
  same time as PB.
• Check quality of the clock
• VME controller R/W test to check VME access,
  reading mother ID, serial number
• TTCrx access
• DCS Fujitsu microcontroller use CANbus protocol
  need C-routines developed by D. Mills to test its
  access

More than happy!
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CP chips Test vectors

• Connectivity same set of vectors for Had and EM
  part
• BC-mux chips in operational mode9 cases of
  BC-mux (TDR) scanned
• Test with adjacent CPM board
• Cluster Processor algorithm tested with Playback
  memory from other CPM.

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Serialiser 1 CP 5 DSS cards

• No playback memory DSS cards
• Connectivity similar vector pattern as for the
  CP 40 bits in input, set BC-mux flag off, 80
  bits in Dual Port Memory
• BC-mux 9 cases of BC-mux scanned
• CP algorithm tested

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H/W debugging

• Testpoints
• Frozen clocks, inputs from 2x8 CP and 20
  serialisers to the ROC, 20 Glinks output, LVL1A,
  Bcrst, Power supply, Load_Shift, more?
• Flexible from FPGA reserves couple of pin
  outputs where interested signals could be routed
  Fifo address, En_Shift, etc

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TimeScale