Addressing the Challenge of Wafer Map Classification in Semiconductor Manufacturing

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Addressing the Challenge of Wafer Map
Classification in Semiconductor
Manufacturing https//yieldwerx.com/
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The field of semiconductor manufacturing is an
intricate and intensive process that involves
numerous complex chemical and physical
operations. The final yield of the process, which
signifies the percentage of functional chips
produced from a silicon wafer, is a primary
measure of a fabrication plant's efficiency.
However, this yield is often affected by a
multitude of factors, including equipment
malfunctions, material impurities, and errors in
process control. Fault detection and
classification play a crucial role in optimizing
the yield of the process. These faults can be
detected and classified by analyzing wafer maps,
which are essentially two-dimensional
representations of each die on a silicon wafer.
The wafer map software display defect patterns
that correspond to issues in manufacturing, with
each defect having a unique signature that
provides clues about the source of the
problem. Machine Learning in Wafer Map
Classification  Recently, there have been
significant efforts to automate the
classification of wafer maps using machine
learning (ML), specifically Convolutional Neural
Networks (CNNs). CNNs are a type of deep learning
model that excels at recognizing patterns in
images. They are trained on previously annotated
wafer maps, and once trained, they can classify
new maps into probable defect categories in real
time. This not only reduces costs but also
minimizes the manual labor involved in
classifying thousands of dies per wafer manually
with the help of die per wafer calculator.
However, a fully automated approach has a
significant drawback. Achieving near-perfect
accuracy in classification, a requirement due to
the high misclassification cost remains a
challenge. Misclassification could potentially
result in a high-value chip being scrapped due to
a false-positive detection or a defective chip
being passed for packaging due to a false
negative, leading to significant financial
losses. A Semi-Automatic Method  To overcome the
limitations of a fully automated approach, a
semi-automatic method of wafer map pattern
classification is proposed. This approach
selectively utilizes the CNN based on its
predictive uncertainty on a given wafer map.
Predictive uncertainty refers to the confidence
that the model has in its prediction. If the
uncertainty is low, indicating that the CNN has a
high degree of confidence in its prediction, the
map is classified using the CNN. Conversely, if
the uncertainty is high, indicating that the CNN
is unsure about its prediction, the map is
classified manually by a process engineer. This
method, designed to improve the accuracy of CNN
in the inference phase, ensures near-perfect
accuracy while maximizing CNN coverage and
minimizing engineering effort. Essentially, it
combines the strengths of automated
classification (speed and scalability) with
manual classification (precision and reliability).
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Experimental Results   Experimental tests were
conducted using the WM-811k dataset, a
large-scale wafer map dataset widely used for
training and evaluating machine learning models
in wafer map classification. This dataset
contains more than 800,000 wafer maps, each
labeled with one of 9 classes representing
different defect types. The results demonstrated
that the semi-automatic method achieved an
impressive accuracy rate of over 99 with a CNN
coverage of 93, meaning that the CNN was able to
confidently classify 93 of the wafer maps, with
the remaining 7 requiring manual classification
by an engineer. This finding represents a
significant improvement over previous efforts,
showcasing the potential of this semi-automatic
approach to deliver high accuracy rates while
reducing the workload of process
engineers. Detailed Overview of Wafer Map
Classification Using CNNs   Convolutional Neural
Networks (CNNs) are a type of deep learning model
that is adept at image recognition tasks, making
them particularly suitable for wafer map pattern
classification. A wafer map, being a visual
representation of a wafer, can be considered as
an image with different pixel intensities
corresponding to the state (functional or
defective) of each die. The CNN model
architecture generally consists of an input
layer, multiple convolutional layers, pooling
layers, fully connected layers, and an output
layer. The convolutional layers are responsible
for feature extraction from the input wafer maps.
These features are then down sampled in the
pooling layers to reduce computation and provide
translation invariance. After several iterations
of convolutions and pooling, the output is
flattened and passed through fully connected
layers for final classification. The output layer
employs a SoftMax function that gives a
probability distribution over the possible defect
classes for a given wafer map. The CNN is trained
using a large dataset of annotated wafer maps,
where the model learns to associate certain
patterns in the wafer maps with specific defect
classes. The performance of the CNN is typically
evaluated using a separate validation set and is
fine-tuned to minimize classification errors.
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The Role of Predictive Uncertainty in the
Semi-Automatic Approach  The concept of
predictive uncertainty is central to the proposed
semi-automatic approach. It refers to the
confidence the CNN has in its prediction for a
given wafer map. A low predictive uncertainty
means that the CNN has a high degree of
confidence in its prediction, and therefore, the
map is classified using the CNN. On the other
hand, a high predictive uncertainty means that
the CNN is unsure about its prediction, leading
to the map being classified manually by a process
yield engineer. Predictive uncertainty can be
estimated in multiple ways. One common approach
is to use dropout at test time, a method known as
Monte Carlo Dropout. By dropping out random
neurons during each forward pass at test time, we
obtain a distribution of predictions from which
we can estimate the model's uncertainty. The
threshold that determines whether the predictive
uncertainty is high or low is a hyperparameter
that can be adjusted based on the requirements
and constraints of the semiconductor
manufacturing process. The Practical Implications
and Benefits of the Semi-Automatic Approach  In
the context of semiconductor manufacturing, the
proposed semi-automatic approach offers several
practical benefits. First, it combines the
strengths of CNNs (speed and scalability) with
those of process engineers (precision and
reliability), enabling high-throughput and
accurate wafer map classification. Second, the
semi-automatic method addresses the challenge of
misclassification, which can lead to significant
financial losses. By utilizing human expertise
when the CNN's predictive uncertainty is high,
the method reduces the likelihood of
misclassification and thus safeguards the
economic viability of the manufacturing process.
Third, the semi-automatic approach can help
manage workforce resources more effectively. By
automating the classification of wafer maps with
low predictive uncertainty, process engineers can
focus their efforts on more challenging cases
that require in-depth analysis, enhancing the
overall productivity of the manufacturing
process. Lastly, by providing an additional layer
of scrutiny for wafer map classification, the
semi-automatic approach helps improve the overall
yield of the manufacturing process. By detecting
and categorizing defects more accurately, process
engineers can better understand the root causes
of these defects and take corrective measures,
thereby optimizing the yield of the process.
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• Conclusion
• In conclusion, the semi-automatic wafer map
  pattern classification method offers an efficient
  solution for achieving near-perfect accuracy in
  semiconductor manufacturing. This method
  successfully manages the high costs of
  misclassification associated with fully automated
  systems, leveraging the strengths of both CNNs
  and process engineers. By harnessing the power of
  AI, we can ensure higher wafer yield, reduce
  wastage, and streamline the semiconductor
  manufacturing process.
•  References
•  
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• Kim, Y. B., Lee, J. W., Kim, T. Y. (2022).
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