IEEE 2015 VLSI FLOATING-POINT BUTTERFLY ARCHITECTURE BASED ON BINARY SIGNED-DIGIT REPRESENTATION.pptx

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FLOATING-POINT BUTTERFLY ARCHITECTURE BASED ON
BINARY SIGNED-DIGIT REPRESENTATION
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ABSTRACT

• Fast Fourier transform (FFT) coprocessor, having
  asigni?cant impact on the performance of
  communication systems, hasbeen a hot topic of
  research for many years. The FFT function
  consistsof consecutive multiply add operations
  over complex numbers, dubbedas butter?y units.
  Applying ?oating-point (FP) arithmetic to FFT
  architectures,speci?cally butter?y units, has
  become more popular recently.It of?oads
  compute-intensive tasks from general-purpose
  processors bydismissing FP concerns (e.g.,
  scaling and over?ow/under?ow).

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• However,the major downside of FP butter?y is its
  slowness in comparison withits ?xed-point
  counterpart. This reveals the incentive to
  develop ahigh-speed FP butter?y architecture to
  mitigate FP slowness. Thisbrief proposes a fast
  FP butter?y unit using a devised FP
  fused-dotproduct-add(FDPA) unit, to compute AB
  CD E,basedonbinarysigned-digit(BSD)
  representation. The FP three-operand BSD adder
  andthe FP BSD constant multiplier are the
  constituents of the proposedFDPA unit.

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• A carry-limited BSD adder is proposed and used in
  thethree-operand adder and the parallel BSD
  multiplier so as to improvethe speed of the FDPA
  unit. Moreover, modi?ed Booth encoding isused to
  accelerate the BSD multiplier. The synthesis
  results show that the proposed FP butter?y
  architecture is much faster than
  previouscounterparts but at the cost of more area.

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EXISTING METHODS

• 1. FFT architecture using fixed point arithmetic,
  which cant support for wide dynamic range of
  operations.
• 2. Usage of redundant number systems is another
  well-known way of overcoming
• FP slowness, where there is no word-wide carry
  propagation withinthe intermediate operations.

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PROPOSED METHOD

• The proposed butter?y architecture is designed
  using redundantFP arithmetic, which is useful for
  FP FFT coprocessors andcontributes to digital
  signal processing applications. Althoughthere are
  other works on the use of redundant FP
  numbersystems, they are not optimized for
  butter?y architecture inwhich both redundant FP
  multiplier and adder are required. Thenovelties
  and techniques used in the proposed design
  include thefollowing.

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• 1) All the signi?cands are represented in binary
  signeddigit(BSD) format and the corresponding
  carry-limited adderis designed.
• 2) Design of FP constant multipliers for
  operands withBSD signi?cands.
• 3) Design of FP three-operand adders for
  operands withBSD signi?cands.
• 4) Design of FP fused-dot-product-add (FDPA)
  units(i.e., AB CD E) for operands with BSD
  signi?cands.

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ADVANTAGES

• High speed is achievedby eliminating extra LZD,
  normalization, and rounding units.