ASIC Development for the SNAP Focal Plane

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ASIC Development for the SNAP Focal Plane

• Natalie Roe
• Lawrence Berkeley National Laboratory
• February 4, 2004

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Outline

• Overview of SNAP Focal Plane Design
• Science driven requirements
• Focal plane design observing strategy
• Electronics design overview
• Visible Imager Readout
• Requirements
• ASIC development program
• Front end design
• Front end test results
• ADC design
• ADC simulation results
• Future plans
• Summary

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Science-Driven Requirements to Instrument Concept

• Instrument
• Space-based for better sensitivity to
  near-infrared light from high-z SNe
• A large FOV (0.7 sq. deg. ).
• Observation cadence commensurate with SNe
  evolution (every 4 days).
• Small PSF, large FOV for weak lensing

• Measurement Program
• Discover SNe early, follow lightcurve to
  determine peak luminosity
• Take spectrum near peak to identify SNe Ia from
  SiII feature at 6150A
• 2000 well measured SNe from z0.3 to 1.7 to
  construct high-statistics Hubble diagram
• Five-month wide-area weak lensing survey (300 sq
  deg) to study dark matter
• gt constraints on Wm, L, w, w

• Simulated 1-year SNAP mission.

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Science-Driven Requirements to Instrument Design

• Photometry
• Measure peak luminosity to 2 relative accuracy -
  in SNe restframe
• Early detection to avoid bias and determine
  explosion date
• Determine initial conditions, control for
  extinction through detailed multi-color
  lightcurves

• Imager
• Wavelength coverage from 350 nm to 1700 nm (9
  filters)
• Two plate scales to cover the wavelength range to
  obtain time efficient photometry.
• Zodiacal light - limited measurements.

SNAP Filter Set
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Instrument Working Concept
Secondary
2m Primary
Focal Plane
Shutter
Tertiary
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Focal Plane Concept
Focus star lamps
Thermal links
Focus star projectors
Guider
Visible (6 filters)
NIR (3 filters)
Spectrograph port
Calibration lamps
Spectrograph
Calibration projectors
Read-out electronics
Operating Temperature 140 K
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Observing Plan

• Repetitive imaging program (60 of time)
• Observe 7.5 square degrees every four days in all
  9 filters, in N S ecliptic
• Multiplexed supernova light curves and discovery
  on the same images.
• Step stare 4 co-added dithered 300 sec
  exposures, with 30 sec readout, then move to next
  filter (NIR filters have 2x area gt 2x exposure)
• Targeted spectroscopy (40of time) near peak

35 pointings to cover 7.5 sq deg
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Electronics Working Concept

• Front-end electronics mounted on back of cold
  plate
• Reduces cable plant, simplifies grounding
  shielding issues, mass
• Minimize cross-talk, pickup for small analog
  signals
• Reduces power consumption due to increase in e-
  mobility
• Avoid problems associated with driver on CCD -
  power, noise
• Compatible with HgCdTe readout being developed by
  Rockwell (SIDECAR ASIC) - must be lt10 cm from
  sensor operate cold
• Thermal constraints - must keep cold plate cold,
  stable
• power budget for sensors co-located
  electronics 15W total
• ASIC development requires RD investment, lead
  time in schedule
• Memory, instrument control unit located in
  shielded room temperature boxes mounted on space
  craft
• Minimize radiation exposure
• Simpler temperature requirement
• No thermal impact on focal plane

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Instrument Electronics Layout
Focal plane
Battery
Instrument Control Unit
Power system
Mass memory
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NIR Electronics

• The Rockwell SIDECAR ASIC provides
• Programmable gain pre-amplification
• 16 bit, 100kHz ADC
• Sequencer Clock pattern generator supporting
  modes of operation erase, expose, readout, idle.
• Bias and power generation
• Currently under development at RSC

Rockwell SIDECAR ASIC
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LBNL IC Engineering Group

• IC group at LBNL has developed ASICs for many
  projects
• Work reported on here today has been carried out
  by
• Henrik von der Lippe (IC Engineering Group
  Leader)
• Jean-Pierre Walder (IC designer)
• Brad Krieger (IC designer)
• Armin Karcher (test engineer)
• undergraduate students
• Design effort started in Fall 2002
• Approx. 2.5 FTE years invested
• First test chip submission in May, 2003 (CDS
  only)
• Second submission planned in March, 2004 (CDS
  ADC)

• ICs Developed at LBNL
• Elefant (BaBar DC FE)
• Atom (BaBar Si Vtx FE)
• SVX, SVXII, SVXIII, SVX4
• (Si Vtx FE for CDF, D0)
• WTA (PET Photo diode readout)
• QMUX (Amorphous Si Xray)
• CDS (Si CCD)
• Café-M (ATLAS Si Vtx FE)
• ABC (ATLAS Si Vtx FE)
• Star (TPC readout - 2 chip set)
• Pixel (ATLAS Pixel FE)
• FPPA (Si APD)
• CTRL (Si APD)
• Arapix64 (Si photo detector)

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CCD Electronics

• CRIC ASIC
• Dual-rampCorrelated Double Sampler with a
  multislope integrator
• ADC 12-bit, 100 kHz equivalent conversion rate
  per CCD output
• Clock Control
• Sequencer Clock pattern generator supporting
  modes of operation erase, expose, readout, idle.
• Clock drivers Programmable amplitude and
  rise/fall times. Voltages 20V

• Bias and power generation Provide switched,
  programmable large voltages for CCD and local
  power. (60-80V)
• Temperature monitoring Local and remote. DAQ
  and instrument control interface

CCD
CRICAnalog readout
13-bit Pipelined ADC
Digital out
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CCD Front end readout requirements

• Low noisePhotometry CCD electronic noise ?
  4e rms (14mV)Spectrograph CCD electronic
  noise ? 2e rms (7mV)
• Large dynamic range96dB from noise floor to
  130ke well depth (16-bit)
• Readout frequency ? 100 kHz 50kHz
• Radiation tolerant 10 kRad ionization (well
  shielded) test to 150 kRad
• Low power ? 200mJ/image/channel gt lt
  10mW/channel
• Operation at 140K and 300KAllow normal operation
  at 140K and chip testing at room temperature
• Compact
• Robust, space qualified

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0.25mm CMOS at low temperature
For both P and N type
Mobility increase
Threshold voltage increase -1mV/K
Measurements performed at the lab
Mobility ratio as a function of temperature
Threshold voltage as a function of temperature
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Signal processing required to reduce noise
Frozen noise charge, with a variance of kTC,
stored in floating diffusion capacitor Cfd just
after reset.
Thermal and 1/f noise of the output transistor
Thermal noise of the output resistor

• Correlated double sampling removes reset level
  and the kTC noise ( ) and reduces 1/f noise (
  )
• Integration reduces the thermal noise ( )

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CCD output noise

• Noise spectral density of CCD output source
  follower (47/6 transistor)
• Critical numbers 1/f Noise1.5 mV/Hz1/2 _at_ 1
  Hz, Thermal Noise20nV/Hz1/2, 3dB roll off _at_
  50MHz

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Signal processing behavioral model
Ideal noisy integrator
CCD conversion gain 3.5mV/e
C
Switch matrix
Out
R
Vn
R1
R2
A3
Vout
R1
Vn
R2
-
R
-
A1
A2
(CDS)

Out-

Vn
C
CCD noise source
Out
(t4ms)
t
t
time
Reset integration
Signal integration
Real integration during 2t. Good rejection of the
CCD thermal noise.
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12 bit Resolution Requirement

• The signal to noise ratio of the sensor plus
  readout chain is limited by the photostatistics
  of the light collection of the CCD
• dN/N 1/ vN where N is the number of
  photons.
• The readout chain can digitize the signal with an
  adjustable gain such that the quantization noise
  is always below the Poisson noise.

Poisson ? electronic noise
0.5 x (Poisson ? electronic noise)
Gain 32
Gain 2
Gain 1
Quantization noise area
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CRIC CDS channel architecture
Control logic
Single to differential stage
CDS
Output buffers
Multi range integrator
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CRIC CDS Test Chip

• Designed, laid out and simulated in LBNL IC
  Engineering group
• 4 CDS channels plus test structures
• Implemented in 0.25 um TSMC CMOS process die
  size 3.6 mm x 5.4 mm
• Fabricated through MOSIS service
• Tested at 140 and 300 K
• Combined test with LBNL CCD
• Radiation testing up to 150 kRad

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Test setup
Reference voltages
16-bit ADCs
16-bit
D
Software controlled operation
A
C
s
(2e/DAC cnt)
Power
LVDS ctrl signals
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Transient response (Full scale signal)
Reset level integration
Data digitized here
Signal integration
Gain 2 indicator bit
Gain 1 indicator bit
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Linearity measurement (100kHz)
Gain 32
Gain 1
Gain 2
1 DAC count 14mV 2e
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Linearity Measured deviation from best fit
Slope 32
Slope 2
Slope 1
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Noise measurement (Slope 32) 100kpx/s
Mean 8787 ADC cnts Rms 14 cnts For Input DAC
8000cnts
Mean 10192 ADC cnts Rms 14 cnts For Input DAC
8100cnts
?Conversion gain 14 ADCcnts/2e (1 DAC cnt
2e) Noise_at_300K 2e- Noise_at_140K 1.6 e- Measured
Power 6.5 mW/channel
100 kpx/s
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Cold, Powered Radiation Testing of CRIC chip

• Test setup
• 1.9 GeV electrons from LBNL Advanced Light Source
  (ALS) injection beam
• Beam diameter 7 mm FWHM
• Two bunches per pulse
• One pulse per second
• Dose accuracy /-50
• Measured with TLD and transformer
• Total exposure 150 kRad (TLD) or 320 kRad (beam
  current)
• CRIC chip powered in 140K dewar for exposure
  tests
• Gain, noise and offset monitored for 4 channels
• No evidence for radiation damage!

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CRIC/ADC block diagram
f1
Start
f2
CCD
CRIC CDS/Integrator
13-bit Pipeline ADC
Y
CCD reset integration
CCD signal integration
4ms
1ms
4ms
Start
4.8ms
Period10ms
f2
f1
4.8ms
Y
500ns
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Analog to digital conversion

• Digitize the analog data coming out of the
  multi-slope integrator.
• The pipelined ADC architecture was chosen. It
  allows digital transitions to occur while the
  analog front-end is blind.

N cells in series for a N-bit ADC
Input
Residue
Input stage
1 Bit ADC
1 Bit ADC
Digital output
MSB
LSB

• Simplest architecture each stage determines one
  bit, subtracts the bit value, then outputs the
  residue with gain x2
• If Vin gt Vref , Vout 2 x(Vin - Vref ), if Vin
  lt Vref , Vout 2 x Vin
• The first stage residue is digitized by an (N-1)
  bit ADC, and so on

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SNAP ADC features

• 13-bit resolution
• 13 pipelined stages
• 1.5bit/stage.
• Integral non-linearity - 0.5 LSB (after
  calibration)
• Differential non-linearity - 0.5 LSB (after
  calibration)
• ADC noise 1 LSB
• Inter-stage gain 2.
• Digital correction (1.5 bits/stage)
• Digital calibration of the 8 first stages (Self
  calibrated).
• Fully differential.
• Switch OTA architecture.
• 4V full scale.
• Readout rate100 KHz.
• Power 3mW.

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13-bit ADC block diagram
Basic 13-bit pipeline ADC architecture
X13
Clock
Input stage
1-bit cell
1-bit cell
D12
D0
Digital output
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13-bit ADC block diagram
X13
Clock
Input stage
1.5bit cell
1.5bit cell
Raw data (26 bits)
Digital correction
D12
D0
Digital output

• Digital correction provides overlap between the
  quantization ranges of adjacent stages by using
  extra comparators (1bit ? 1.5bit)
• This systematic correction provides a correction
  of comparator offset .

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13-bit ADC block diagram
Digital calibration takes care of mismatches,
finite DC gain of the 1.5-bit cell components.
Only the first stages are calibrated (8 in our
case).
X13
Clock
Input stage
1.5bit cell
1.5bit cell
Raw data (26 bits)
Digital calibration
Digital correction
Corrected data (13 bits)
Digital subtraction
D12
D0
Digital output
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Linearity with Calibration Correction
Without correction
With correction
(simulation)
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ADC Status Plans

• ADC design is complete, Preliminary Design Review
  passed
• Layout in progress
• Also implementing minor modifications to CDS
  chip, adding band-gap reference circuit to
  provide Vref
• Submission planned for March 22 to TSMC 0.25 um
  process through MOSIS
• CDS ADC CRIC2 chip will be tested at 140 and
  300 K, radiation tested, and eventually packaged
  together with SNAP v. 1 CCD for module testing

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Summary
Summary

• A low power, 16-bit dynamic range, 12-bit
  resolution multi-range CDS signal processor has
  been integrated for the SNAP CCD readout and
  successfully tested.
• Performance summary
• Noise
• 300K 2.0e- _at_ 100kHz, 1.5e- _at_ 50kHz
• 140K 1.6e- _at_ 100kHz, 1.33e- _at_ 50kHz
• Linearity 12-bit for all ranges
• Gain(T) 400ppm/K
• Dynamic range 16-bit
• Readout speed 100kHz 50kHz
• Power 6.5mW/channel
• Irradiation tests at 140K have been performed
  with good results
• A low-power 13-bit pipeline ADC, digitizing the
  signal coming out of the multi range integrator
  has been designed and submission of combined CDS
  ADC is planned for March
• Eventually will mount CRIC chip together with
  LBNL CCD for photons to bits package