Interconnect Focus Center

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MICROPHOTONIC INTERCONNECTS
Lionel C. Kimerling, MIT
Other principal investigators M. F. Chang,
UCLA E. A. Fitzgerald, MIT J. S. Harris,
Stanford D. A. B. Miller, Stanford P. Persans,
RPI
Optical and RF technologies for on-chip and
off-chip interconnection and clock distribution
to provide a scalable platform for bandwidth,
signal integrity and synchronization.
Interconnect Focus Center
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ECONOMIC AND PHYSICALLIMITS TO TECHNOLOGY

• Computation is now a commodity
• CMOS dimensional scaling
• speed, power, cost
• Communication is the scarce quantity
• End-to-end optical networking
• Chip-level optical interconnection

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Microprocessors 2010
?

• 100 Tb/s on-chip
• 40 Tb/s off-chip
• 1010 grids
• Collaborative

• 5000 pins
• Low latency
• Low power
• Low crosstalk

3 GHz off-chip and global clock rates 10 GHz
local clock rates
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MICROPHOTONICSA Disruptive Technology

• Sales growth of at least 100x/decade
• Market penetration by scalability
• Functionality
• Performance
• Yield
• Cost

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The Scaling Law Index Contrast
2001
Si3N4
Si
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Single Mode SiOxNy Waveguides
Goal develop and evaluate the material,
deposition methods and parameters and
architectures to enable fabrication of single
mode optical waveguides for PLCs.

• Major tasks
• Design of properties range for single mode
  confinement
• Optimize parameters for minimizing polarization
  dependent losses
• Develop standard architectures and layouts
• Evaluate deposition methods (Sputter Deposition,
  PECVD, LPCVD)
• Develop characterization methods and tools
• Integrate waveguides with photodetectors

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Index Tuning of Sputtered Films
Refractive index is a linear function of the
oxygen flow rate into the chamber.
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OPTICAL BUS ARCHITECTURE

• chip testing
• clock distribution
• on-chip I/O
• MCM/PWB architectures
• ethernet I/O

Optical Signal Distribution
off-chip source
waveguides (polySi)
splitters and bends
photodetectors (Ge)
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MONOLITHIC SILICON MICROPHOTONICS
Kimerling Group, MIT
APPROACH To create technology building blocks
under the constraints of the conventional silicon
fabline, IC design and systems performance
requirements.

• ACHIEVEMENTS
• Low loss Si nanowaveguides
• Integrated SiEr LED / CMOS driver
• Microresonator devices and circuits
• 16x fanout clock signal
• Vertically coupled architectures
• Ge on Si photodetectors
• Wafer bonded isolation/integration

R890 mA/W with AR Coating
t 180pS (100x100mm)
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Silicon Racetrack Response
Fabricated by 248nm Lithography Q 2000, FSR16
nm
Silicon
Silica
6 um
Drop
In
Haus, Lim, Maki and Kimerling, MIT
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High Order Microring Filters(Silicon Nitride)
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Dislocation Free, Ge Photodetectors (direct
growth of Ge on Si)
Ge
SiO2
SiO2
SiO2
Si
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Monolithic Ge-on-Si Photodetector Performance
t 180pS
-V
nGe
V
Ge
pSi
330 mA/W with 1 mm Ge 550 mA/W with 4 mm Ge 890
mA/W with AR Coating
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I/O APPLICATION 1x4 WDM in Silicon Nitride
Efficiency 100, Q500
Thru-port
Thru-port
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2
3
4
Lim, Little, Maki, Haus and Kimerling, MIT
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INTEGRATED SOURCES Monolithic
III-V on Si
Room-temperature, continuous-wave 850 nm GaAs
laser on SiGe/Si
Fitzgerald Ram, MIT
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CLOCK DISTRIBUTION

• ELECTRICAL
• Frequency over distance
• Jitter 5 of period
• 10pS for 10GHz
• Skew 5-20 of period
• within die variations
• EMI
• Power dissipation

• OPTICAL
• Bandwidth over distance
• Jitter 12pS fiber demo
• laser stability
• Skew equal distance tree
• receiver circuit variation
• EMI no effect
• Power off-chip source

Ian Young, Intel
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Optical Clock Signal Distribution
optical clocking source

• Key issues
• Small bending radius for on-chip application
• Equal power distribution (49.5/50.5)
• Efficient coupling of light (lt1.7dB)
  (fiber/waveguide waveguide/detector)
• High detector responsivity and fast rise time

Optcial receiver (photodetector/TIA)
local Electrical H-tree distribution
Tasks I, II, III (with Chandrakasan, Boning at
MIT)
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SiON Waveguide Design
16 fanout H-tree structure
Bending radius 250mm
Preliminary results

• PECVD deposited
• Design Criteria
• 16X fanout, ? 850nm, a1?10-8mm-1

Measured 1.7dB along 3.5mm
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Baseline Optical Receiver
Vbias
Post Amplifier
Preamplifier
LPF

• 0.35mm baseline design operates at 1GHz

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Preliminary Results Latency
3
2.5
0.25mm (1.5V)
2
0.25mm (3V)
Delay
1.5
1
Optical
0.5
0
2
6
10
14
18
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Wire Length in Millimeters

• Electrical solution uses optimal buffering

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Variation-Aware Optical Clock Receiver
Goal Design of optical receiver circuits with
special emphasis on variation robustness
Clock Receiver - Version 1

• Transimpedance preamplifier
• Inverter-based cascade with feedback biasing
• Highly sensitive to variations in power supply
  voltage

S. Sam (Boning Chandrakasan, MIT)
0.35 um CMOS Technology
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Optical Clock Receiver Design

• Key Lessons
• Version 1 showed that premature clipping creates
  skew, and employed feedback biasing to compensate
• Version 2 used better feedback biasing and
  voltage supply regulation to maintain symmetric
  clipping, but found that process variations (VT
  and channel length) are hard to design around
• Version 3 Design Goals (N. Drego)
• Reducing variation effects
• Maintaining constant duty cycle
• Reducing overall size and power consumption
• Differential signaling makes clipping more
  symmetric
• Additional feedback biasing in transimpedance amp
  to reduce sensitivity to input power signal

M. Mills and N. Drego (Boning, MIT)
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MICROPHOTONIC CONNECTIVITY THE ECONOMICS OF
INTEGRATION
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Electronic/Photonic Convergence
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The Future of Communications

• Photonic functionality
• Microphotonics, Optical Signal Processing
• High yield, low cost manufacturing
• Standardization
• Bandwidth to the User
• Photons-to-the-Information Appliance
• Incumbents vs. Small Companies
• Building the Photonic Infrastructure