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MVSIS

- MVSIS Group
- Minxi Gao,, Jie-Hong Jiang, Yunjian Jiang,

Yinghua Li, Subarna Sinha and Robert K. Brayton - Dept. of Electrical Engineering and Computer

Science University of California, Berkeley

Outline

- Motivation From binary to multi-value
- Design specification
- MVSIS optimizations
- Node simplification
- Kernel and cube extraction
- Pairing and encoding
- Network manipulation
- Demo
- Conclusions

History

- Multi-valued logic

Incomplete references

E. L. Post, Introdution to a general theory of

elementary propositions,Amer. J. Math., Jun 1921

J. C. Muzio and D. M. Miller, On the

minimization of many-valued functions,Proc. 9th

Int. Symp. Multiple-valued Logic, 1979

S. L. Hurst, Multiple-valued logic its status

and its future, IEEE Trans. On Computers, Jun

1984

J. C. Muzio and T. C. Wesselkamper,

Multiple-valued switching theoryBristol

Hilger, 1986

R. K. Brayton and S. P. Khatri, Multi-valued

logic synthesis,Proc. 12th Int. Conf. On VLSI

Design, Jan 1999

Motivations

- Synchronous hardware synthesis
- Software synthesis from synchronous

specifications - Asynchronous hardware synthesis
- Multi-valued devices?
- Current-mode CMOS devices
- Optical logic circuits

Motivation synchronous hardware

- Design and synthesis from multi-valued logic
- Natural method of specification
- Larger design space

Verilog-MV

vl2mv

BLIF-MV

Two-level MV-PLA synthesis R.Rudell, et al

Espresso-MV, 1987

MV-Optimize

Multi-level FSM synthesis (single MV) L.Lavagno,

et al MIS-MV, 1990

Opt-Encode

Encode

FSM state encoding T.Villa, et al, Nova,

1990 E.Goldberg, et al, Minsk, 1999

MVSIS

SIS

Motivation software synthesis

- Synchronous programming of embedded systems
- Esterel/Lustre/Signal
- Interactive FSM semantics
- Code generation from logic

FSMs

POLIS F.Balerin, et al, Synthesis of software

programsfor embedded control applications, TCAD

1999

MV-Optimize

ESTEREL G.Berry, The foundations of Esterel,

2000

Code Gen

POLISVCC

MVSIS

MVSIS Y.Jiang, et al, Logic optimization and

code generationfor embedded control

applications, CODES 2000

C/Assembly

Motivation multi-valued devices

- Multi-valued current-mode MOS
- signed digit arithmetic
- High-speed, Low supply voltage

Building blocks

Iy

Ix

IT

x

y1

y2

T. Hanyu and M. Kameyama, A 200 MHz pipelined

multiplier using 1.5 V-supplymultiple-valued MOS

current-mode circuits with dual-rail

source-coupled logic, IEEE Journal of

Solid-Statee Circuits, 1995

Functional Semantics

F

- Network of MV-nodes
- Each variable xn has its own range0, 1,,

Pn-1 - Values are treated uniformly
- MV-literal X0,2
- MV-cube X0,2Z0,1
- MV-function

Latch

Design Specification

.model simple .inputs a b .outputs f .mv f 3 .mv

x 3 .table x a b -gt f .def 0 0 1 1 1 1 0 - 1 1

1 1 2 0 - 0 2 .reset x 0 .latch f

x .exdc .inputs a b .outputs f .table a b -gt

f .def 0 0 0 1 .end

- BLIF-MV subset
- Deterministic (no pseudo inputs)
- Single output MV nodes
- Flat network, no hierarchy
- Constant initial states (.reset)
- Extension
- External dont care networks (.exdc)

MVSIS Optimization

- MVSIS optimizations
- Node simplification
- Kernel and cube extraction
- Pairing
- Encoding
- Network manipulations

Node Simplification

a b c d z

100 11 011 101 0 101 10 111 011 0 110 10 110

110 0

100 11 111 101 1 111 01 100 111 1 100 11 110

110 1

- Two-level Espresso-MV
- Multi-level

ltdefaultgt 2

101 01 100 001 - 010 01 001 101 -

Minimize each i-set independently Dont care

input minterm that produces all output

values Partial care input minterm that produces

a subset of output values

Compatible observability dont cares(CODC) Satisf

iability dont cares (SDC) External dont cares

(XDC)

mvsisgt simplify mvsisgt fullsimp mvsisgt

reset_default

Algebraic Decomposition

M. Gao and R. K. Brayton, Multi-valued

Multi-level Network Decomposition, IWLS, June

2001.

- Kernel extraction
- Semi-algebraic division
- Resubstitution
- Factoring/Decomposition

F a0,1,2 b0,1,2,3c3 b1,2,3 c3

a0b1,2,3 c0 a0 b0,1,2,3c1

-q Two-cube divisors -g Best divisors

(c3 a0c0,1)(a0,1,2 c1,3 b1,2,3

c0,3)

mvsisgt fx -q -g mvsisgt decomp mvsisgt

factor mvsisgt resub

Pairing and Encoding

- Pair_decode/Merge
- Encode
- Merge some i-sets

Bit-pairing to create multi-valued node Explore

different encodings

SOP further simplified Output literal count

reduced

mvsisgt pair_decode mvsisgt merge mvsisgt

encode mvsisgt elim_part

Other Commands

- Network manipulations
- IO interface
- Verification

- Printing
- Sequential

mvsisgt eliminate mvsisgt collapse Mvsisgt sweep

mvsisgt print_stats mvsisgt print_factor mvsisgt

print_range mvsisgt print_io mvsisgt

print_value mvsisgt print_part_value

mvsisgt read_blifmv mvsisgt read_blif mvsisgt

write_blifmv

mvsisgt extract_seq_dc

mvsisgt validate m mddsimu mvsisgt

gen_vec mvsisgt simulate mvsisgt qcheck

Design Flow

- Typical design flow

mvsisgt source mvsis.script mvsisgt encode

-i mvsisgt source mvsis.scriptb

Example 1

- Matrix multiplication (3 values)

.table a21 a22 b12 b22 c22 0 0 - - 0 0 1 - -

b22 0 2 - 0 0 0 2 - 1 2 0 2 - 2 1 1 0 - -

b12 1 1 0 0 0 1 1 0 1 1 1 1 0 2 2 1 1 1 0

1 .end

2 X 2 matrix mult over the ring Z_3 .model

matmul .inputs a11 a12 a21 a22 .inputs b11

b12 b21 b22 .outputs c11 c12 c21 c22 .mv

a11, a12, a21, a22 3 .mv b11, b12, b21,

b22 3 .mv c11, c12, c21, c22 3 .table a11

a12 b11 b21 c11 0 0 - - 0 0 1 - - b21 0 2 - 0

0 0 2 - 1 2 0 2 - 2 1 1 0 - - b11 1 1 0 0

0 1 1 0 1 1 1 1 0 2 2 1 1 1 0 1 .table a11

a12 b12 b22 c12 0 0 - - 0 0 1 - - b22 0 2 - 0

0 0 2 - 1 2 0 2 - 2 1

1 0 - - b12 1 1 0 0 0 1 1 0 1 1 1 1 0 2 2

.table a21 a22 b11 b21 c21 0 0 - - 0 0 1 - -

b21 0 2 - 0 0 0 2 - 1 2 0 2 - 2 1 1 0 - -

b11 1 1 0 0 0 1 1 0 1 1 1 1 0 2 2 1 1 1 0

1 1 1 1 1 2 1 1 1 2 0 1 1 2 0 2 1 1 2 1 0 1 1

2 2 1 1 2 0 0 0 1 2 0 1 2 1 2 0 2 1 1 2 1 0

1 1 2 1 1 0

cadntws11/home/wjiang/mvsis/examples/bob

mvsis UC Berkeley, MVSIS 0.95 (compiled 24-May-01

at 219 PM) mvsisgt help alias

chng_name collapse

decomp delete

echo elim_part

eliminate encode

extract_seq_dc factor

fullsimp fx

gen_vec help

history

merge pair_decode

print print_altname

print_factor print_io

print_level

print_part_value print_range

print_stats print_value

qcheck quit

read_blif read_blifmv

reset_default reset_name

resub runtime

set

simplify simulate

source sweep

unalias undo

unset usage

validate

write_blifmv mvsisgt

mvsisgt read_blifmv matmul-c mvsisgt

mvsisgt chng_name changing to short-name mode

mvsisgt print_stats matmul 4 nodes, 4 POs, 128

cubes(sop), 480 lits(sop) mvsisgt

mvsisgt print_io primary inputs a b c d e f g

h primary outputs i j k l mvsisgt

mvsisgt set autoexec pfs matmul 4 nodes, 4 POs,

128 cubes(sop), 480 lits(sop), 216

lits(fact.) mvsisgt

mvsisgt print_range i 3 j 3 k 3 l 3 a

3 b 3 c 3 d 3 e 3 f 3 g 3 h 3 matmul 4

nodes, 4 POs, 128 cubes(sop), 480 lits(sop),

216 lits(fact.) mvsisgt

mvsisgt simplify matmul 4 nodes, 4 POs, 96

cubes(sop), 320 lits(sop), 160

lits(fact.) mvsisgt

mvsisgt reset_default matmul 4 nodes, 4 POs,

96 cubes(sop), 320 lits(sop), 160

lits(fact.) mvsisgt

mvsisgt fullsimp matmul 4 nodes, 4 POs, 96

cubes(sop), 320 lits(sop), 160

lits(fact.) mvsisgt

mvsisgt pair_decode 1 m0 a0e2 e0 m1

a0e1 m3 a1e2 a2e1 n0

a0f2 f0 n1 a0f1 n3 a1f2

a2f1 o0 e0c2 c0 o1

e0c1 o3 e1c2 e2c1 p0

f0c2 c0 p1 f0c1 p3 f1c2

f2c1 q0 b0g2 g0 q1

b0g1 q3 b1g2 b2g1 r0

b0h2 h0 r1 b0h1 r3 b1h2

b2h1 s0 g0d2 d0 s1

g0d1 s3 g1d2 g2d1 t0

h0d2 d0 t1 h0d1 t3 h1d2

h2d1 matmul 12 nodes, 4 POs, 64

cubes(sop), 184 lits(sop), 160

lits(fact.) mvsisgt

mvsisgt simplify matmul 12 nodes, 4 POs, 56

cubes(sop), 96 lits(sop), 96 lits(fact.) mvsisgt

mvsisgt reset_default matmul 12 nodes, 4 POs,

56 cubes(sop), 96 lits(sop), 96

lits(fact.) mvsisgt

mvsisgt fullsimp matmul 12 nodes, 4 POs, 56

cubes(sop), 96 lits(sop), 96 lits(fact.) mvsisgt

mvsisgt print_factor i1 m2q2 m1q0

m0q1 i2 m2q0 m1q1

m0q2 j1 n2r2 n1r0

n0r1 j2 n2r0 n1r1

n0r2 k1 o2s2 o1s0

o0s1 k2 o2s0 o1s1

o0s2 l1 p2t2 p1t0

p0t1 l2 p2t0 p1t1

p0t2 m0 a0 e0 m2 a2e1

a1e2 n0 a0 f0 n2 a2f1

a1f2 o0 c0 e0 o2 c2e1

c1e2 p0 c0 f0 p2 c2f1

c1f2 q0 b0 g0 q2 b2g1

b1g2 r0 b0 h0 r2 b2h1

b1h2 s0 d0 g0 s2 d2g1

d1g2 t0 d0 h0 t2 d2h1

d1h2 matmul 12 nodes, 4 POs, 56

cubes(sop), 96 lits(sop), 96 lits(fact.) mvsisgt

mvsisgt validate -m mdd matmul-c Networks are

combinationally equivalent according to MDD

method. matmul 12 nodes, 4 POs, 56

cubes(sop), 96 lits(sop), 96 lits(fact.) mvsisgt

cadntws11/home/wjiang/mvsis/examples/bob

mvsis UC Berkeley, MVSIS 0.95 (compiled 24-May-01

at 219 PM) mvsisgt mvsisgt read_blifmv

red-add.mv mvsisgt

mvsisgt chng_name changing to short-name

mode mvsisgt

mvsisgt print_io primary inputs a b c d

e primary outputs f g h mvsisgt

mvsisgt set autoexec pfs red_adder 3 nodes, 3

POs, 48 cubes(sop), 240 lits(sop), 69

lits(fact.) mvsisgt

mvsisgt reset_default red_adder 3 nodes, 3 POs,

48 cubes(sop), 240 lits(sop), 69

lits(fact.) mvsisgt

mvsisgt simplify red_adder 3 nodes, 3 POs, 15

cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt

mvsisgt fullsimp red_adder 3 nodes, 3 POs, 15

cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt

mvsisgt print_range f 2 g 2 h 2 a 8 b 8

c 8 d 8 e 8 red_adder 3 nodes, 3 POs, 15

cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt

mvsisgt encode red_adder 3 nodes, 3 POs, 15

cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt

mvsisgt print_range f 2 o 2 g 2 p 2 h

2 q 2 i 2 r 2 j 2 s 2 k 2 t 2 l 2 u

2 m 2 v 2 n 2 w 2 red_adder 3 nodes, 3

POs, 15 cubes(sop), 44 lits(sop), 28

lits(fact.) mvsisgt

mvsisgt simplify red_adder 3 nodes, 3 POs, 15

cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt

mvsisgt fullsimp red_adder 3 nodes, 3 POs, 15

cubes(sop), 44 lits(sop), 28 lits(fact.) mvsisgt

mvsisgt print_io primary inputs i j k l m n o p

q r s t u v w primary outputs f g

h red_adder 3 nodes, 3 POs, 15 cubes(sop),

44 lits(sop), 28 lits(fact.) mvsisgt

mvsisgt read_blifmv red-add.mv red_adder 3

nodes, 3 POs, 48 cubes(sop), 240 lits(sop),

69 lits(fact.) mvsisgt

mvsisgt help encode Feb 16, 2001

MVSIS(1)

encode -i -n -s Encode the whole

network into a binary one, considering both

output and input constraints. For

sequential networks, a latch is encoded with

constraints generated from both its inputs and

outputs -i keep primary inputs and

outputs as multi-valued add interface

nodes between the internal encoded binary network

and PI/POs. This option allows

validation of the result. -n use natural

code -s use NO_COMP rather than ESPRESSO

as the intermediate minimization

method. The difference is only in performance.

Ordinary users should not be concerned

with this option. red_adder 3 nodes, 3 POs,

48 cubes(sop), 240 lits(sop), 69

lits(fact.) mvsisgt

mvsisgt encode -n red_adder 3 nodes, 3 POs,

1251 cubes(sop), 9432 lits(sop), 577

lits(fact.) mvsisgt

mvsisgt simplify -t 1000 red_adder 3 nodes, 3

POs, 315 cubes(sop), 2010 lits(sop), 156

lits(fact.) mvsisgt

mvsisgt simplify -t 1000 -m exact red_adder 3

nodes, 3 POs, 300 cubes(sop), 1989 lits(sop),

130 lits(fact.) mvsisgt

mvsisgt validate -m mdd red-add-bin.mv Networks

differ on (at least) primary output s1 i-set

0 Incorrect input is 0 x1_b0 1 x1_b1 1 x1_b2 0

x0_b0 0 x0_b1 0 x0_b2 0 y1_b0 0 y1_b1 0 y1_b2 0

y0_b0 0 y0_b1 0 y0_b2 0 cin_b0 0 cin_b1 0

cin_b2 Networks are NOT combinationally

equivalent. red_adder 3 nodes, 3 POs, 300

cubes(sop), 1989 lits(sop), 130

lits(fact.) mvsisgt

Conclusions

- Multi-valued logic important in various

applications - Presented MVSIS, an multi-valued logic synthesis

software infrastructure - Release 1.0 on Linux platform (as of June, 2001)
- Support registers
- Support external dont care networks
- External dont cares from incomplete

specification - Sequential dont care extraction
- Verification based on MDD representations
- Bug fixes

http//www-cad.eecs.berkeley.edu/Respep/Research/m

vsis