Testing Status Report in NTHU

1
Testing Status Report in NTHU

• SOC Test Integration and Test Schedule
• Produce the DFT and TAM scheme automatically
• Automatically generate test schedule for the IP
  core
• Embedded Memory BIST and Diagnosis
• Automatically diagnosis according to test result
• Memory BIST with diagnosis function
• Embedded Memory Access Time Measurement
• Concurrent measurement with the March Test

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STEAC SOC Test Aid Console
HDL Designs with DFT information
Verilog Parser
STIL Parser
Core Test Scheduler
TACS Generator
TAM Generator
Wrapper Generator
Test Insertion
Wrapper Pat. Trans.
System Pat. Trans.
Testable HDL Designs
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Core Test Scheduling

• Objective
• To schedule core tests for minimum SOC test time
  under given constraints
• To assign optimized TAM resources for each IP
  core
• Given constraints
• TAM architecture and test controller
• TAM width
• Test power
• Core test information

4
TAM Architecture

• Hybrid TAM architecture
• Mixed multiplexed and distributed structure
• Session-based test scheduling

Test Width
Test Time
TAM Source
TAM Sink
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CP Experimental Results

• 1 RSA, 2 AES, 2 HMAC and 1 RNG cores
• Scan chain is re-balanced
• Area

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TAM Width
RSA
AES
AES
HMAC
HMAC
Test Time
235510
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Memory Diagnosis

• Cause-effect analysis
• Fault simulator predicts the faulty responses of
  each fault and constructs March Dictionary
• Looking up the actual responses in the March
  Dictionary

E0
E1 E2
E3
E4 E5
E6 E7
E8 E9
E10
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Diagnosis Support

• The BIST circuit scans out the error information
  (operation, address, signature) during the
  diagnosis mode

8
BRAINS GUI

• A BIST compiler for embedded memories

9
Memory Access Time Measurement

• Concurrent measurement with the March Test

• Based on the March C algorithm
• ?(W0) (to initialize), ?(R0, W1, R1),
• ?(R1, W0, R0), ?(R0, W1, R1), ?(R1, W0, R0)
• One measurement per three cycles

W1 R1 R0 W1 R1 R0
W1 R1 R0
Clock Enable Acc. time Meas.
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Result

• The measurement range is 15ns
• Record the maximum response time
• The core area in a 0.35 ?m 1P4M CMOS technology
  is 262x92?m2

8 bit ripple counter
Capacitors
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Future Works

• Test circuitry insertion and test pattern
  translation
• SOC test integration tool chains wrapper
  generator, core test scheduling, test controller
  generator, and pattern translator
• Memory built-in self-repair