Power Estimation Strategies for A LowPower Security Processor

1
Power Estimation Strategies for A Low-Power
Security Processor

• Y.F. Lee, S.-Y. Huang, et. al
• Design Tech. Center, NTHU
• S.-Y. Hsu, I-Ling Chen
• ITRI, Taiwan
• ASP-DAC 2005

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Introduction

• The accurate power estimation is often necessary
  for the early stages of a low-power design cycle
• The strategies are

3
Background

• Power dissipation in CMOS circuit
• Steady state transition power
• Zero-delay model, state changing of signals
• Hazardous power
• Glitching power
• Different arrival time of inputs
• Short-circuit power
• Direct path from Vdd to the GND, occur when the
  inputs of a gate change slowly
• Leakage power
• Static leaking current associated with a MOS
  transistor

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Previous works

• Average power estimation
• Static probability-based methods no need func.
  vectors
• Dynamic simulation-based methods need func.
  vectors
• Latter one, using Quick-SPICE simulation, is more
  accurate but takes time
• Peak power estimation
• Static approach
• Predict the maximum number of logic gats that
  could switch at the same time and then derive
  upper bounds (sdf file)
• Dynamic approach
• Apply vectors to get lower bounds
• The range is often too loose
• Memory block
• Memory compiler report the read current and write
  current
• Too pessimistic, over-estimation

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Proposed Average Power Estimation

• Total toggle count in Logic simulator
  (Verilog-XL, VCS) to the total power dissipation
  number in Quick-SPICE simulator (PowerMill,
  NanoSim) under the same set of input patterns is
  referred to as a-ratio
• Observation- very slightly changes with the
  patterns

e.g.50
Published in ISLPED96
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Improvement

• Diversity of a-ratio in multi-core design
• C6288 1.7
• C7552 0.6

• Paths that arrive at a gate at different times
• Gates output loading

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Grouping Algorithm

• Logic gates with similar a-ratios are grouped
  together
• Note that- No need knowledge of the design
  hierarchy or designers intervention
• Disparity path number (DPN)
• Max level of Gs inputs min level of Gs
  inputs
• Which is computed by topological order
• Step1
• Different DPN forms different group (contain
  several gates)
• Step2
• Divide each group into several sub-groups based
  on output loading

End of proposed average power
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Proposed Peak Power Estimation

• Power noise analysis caused by excessively large
  current has become important to ensure
  performance and reliability in DSM design
  maximum instantaneous current (MIC)
• Idea identify gates which switch mutually
  exclusively
• Assume gate delay all equals to 1, g1(0,1) ,
  g2(1,3)

G (earlier arr. time, latest arr. time)
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Cont
Published in ICCAD04
End of proposed peak power
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Summary so far

• Average power
• Can use zero-delay model, multiply by a-ratios,
  to achieve close to real power dissipation value,
  which includes hazardous power in consideration
• Peak power
• Can use sdf file (not zero-delay) to identify
  gates which are switching mutual exclusively
• Adding up all gates current which have
  possibility switch at the same time to get MIC as
  upper bounds

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Proposed Memory Power Estimation

• Previous treat memory power as a fixed number
  value for write-mode and read-mode, which is
  generated by commercial memory compilers
• Based on theses power models, one can compute the
  total power dissipation by counting the number of
  memory read and write accesses
• We built such a simple program to run on a memory
  blocks in JPEG2000 encoder shows that it is only
  47 of what reported in a commercial tool

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Cont

• Close look to 4096x16 SRAM block
• Traditional model ignores the dependence on the
  input data lines and address lines

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Which one affects the power more?

• Address lines win!

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Idea
End of proposed memory power
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Experimental Results
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Cont

• end