Design, Synthesis

1
Design, Synthesis Verification of an 8-bit
Microcontroller Core

• Priyank Kalla Dereck Fernandes
• Dept. of Elec. Comp. Engineering
• University of Massachusetts Amherst, USA

2
Project Status

• RTL Design of Microcontroller Core completed
• Instruction Decoder, ALU, PC Stack Implemented
• Memory, Address Decoding, Data Address Buses
• Status Registers and Memory Designed
• RTL Validation of the Design completed
• Validation via simulation Component System
• Validation via simulation Assembly program
• Synthesis of Design partially completed
• Commercial tools (Xilinx) Entire Design
  synthesized
• In-house tools ALU IDEC synthesized
• Formal verification of overall design remains

3
PRAM
Clk
STACK 2
STACK 1
1
R
PC
IDEC
Idec signals
Cwe fwe
B
fwe
addr
K
STATUS
MUX
wwe
DBUS
Data Memory
ALU
Reg W
MUX
1
K
MUX
SBUS
4
Component Design Validation

• Validation of individual components
• ALU
• All arithmetic logic operations
• SAT tools to validate carry, zero and status
  flags
• IDEC
• Each instruction validated, all signals attested
• PC Stack
• Assembly program to validate PC STACK
• Memory Reads and Writes Validated
• Used PIC-micro simulator to validate test programs

5
FPGA Synthesis

• Xilinx Foundation Series Synthesis Tools
• Performed Hierarchical Synthesis
• Mapped onto XCV150-type device.
• Synthesized for Area Delay
• Synthesized for 20MHz (achieved 40MHz).
• Using BDD-Based FPGA Synthesis Tools
• Synthesized ALU Instruction Decoder
• Cannot synthesize memory Synthesis of top-level
  design remains to be done.

6
Synthesis Results Comparisons
7
To Be Completed..

• Synthesis using BDS-PGA Top-level CPU module
• Verification of Synthesized Designs
• Using simulation vectors generated at RTL
• Using test programs in assembly
• Equivalence Verification of synthesized
  components
• Pre-synthesized and post-synthesized netlists.
• Model Checking? If time permits.
• For PC and Stack?
• Project report writing sundries.