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BCM Update

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The Beam Current Monitoring system appears to be in good shape. ... High current driver has a rise time of 1.6 usec, too long for good amplitude meas. ... – PowerPoint PPT presentation

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Title: BCM Update


1
BCM Update
  • Kesselman

2
OUTLINE
  • Findings/Response to FDR held for HEBT, Ring,
    RTBT Systems at BNL 7-22-02
  • Specs/Preliminaries
  • Status
  • Over-view of BCM electronics

3
FDR (7-22-02) Committee Comments and Responses - 1
BCM should be part of the Machine Protection
System Response This is not in the base-line.
It is a requirement for machine protection at low
energy and there will be a discussion session on
Thursday afternoon. The Beam Current
Monitoring system appears to be in good shape.
Problems with cables and connectors. Response
Installation procedure implemented by ORNL.
The PCI data acquisition card (also used for the
BPMs) is not yet finalized. Response Done
The calibrate module is not yet
finalized. Response Bergoz has provided
transformer failure mechanisms. A fused driver
is under consideration. More to follow.
4
FDR (7-22-02) Committee Comments and Responses - 2
       

A bandwidth-limiting filter should be placed in
front of the BCM amplifiers to avoid problems
caused by out-of-band high frequency
signals. Response An input capacitor has been
added to limit system bandwidth to 100MHz.
There is apparently evidence of a 600 to 700 MHz
resonance in the BCM shroud. Consider placing
distributed series RC elements across the ceramic
gap to shunt high frequency beam image
currents. Response Noted. Measurements
indicate minor peak and not a concern. New
design reduces volume.
5
FDR (7-22-02) Committee Comments and Responses - 3
The shroud and its connections to the beam tube
should be designed and tested to handle SNS 50
amp current. Response New design uses no
fingers to carry current and this is no longer
a concern (design to be shown later). The FPGA
should be programmed to not allow nonsense
settings. Response Agree and implemented
6
FDR (7-22-02) Committee Comments and Responses - 4
Software should verify the integrity and
sensibility of measurements, e.g. check for
saturation that may result from incorrect gain
settings. Response We will incorporate such
software. Inclusion of the Alterra FPGA will
permit appropriate logic to be added to assure
correct gain settings. User requirements for
beam current monitoring information seem to still
be lacking. Response Being dealt with at
applications level
7
Major Milestones
  • DTL 1st week in May 03
  • Present perception is a 6 week slip
  • Ring Hardware Late Jan 04
  • On schedule

8
Schedule
9
SNS DESIGN PARAMETERS
  • Energy..1 GeV
  • Intensity... 1.5 x 1014 protons
  • Repetition Rate.....60 Hz
  • Number of Bunches..... 1
  • Injection duration. 1.0 msec
  • Revolution Period.. 945 nsec
  • Bunch Length.... 695 nsec
  • Number of turns. 1060

10
BCM Requirements
  • From SNS Diagnostics AP Requirements (11/05/02)
  • MEBT to HEBT 0.3 - 1000 us,
  • 15 to 52mA
  • Accuracy lt 1 of FSR
  • Resolution 0.5 of FSR
  • Detail within mini-pulse- available on demand
  • Ring to RTBT 5e10 to 2e14 Protons
  • 0.015A to 100A
  • Accuracy lt 1 of FSR
  • Resolution 0.5 of FSR
  • Turn-by-turn data- available on demand
  • Interpretation of requirements

11
Beam Current Monitor Distribution
12
System Electronics Configuration
DFE
PCI DAQ
Event Link
XFMR
Memory or FIFOs
AFE
TIMING MODULE
DACs ADCs
RTDL
XFMR
16 MHz Reference
40 MHz/68MHz LO
CLK
GAIN
CONTROL
CAL
PCI BUSS
CONTROL SYSTEM
RACK MOUNT PC
LabVIEW
13
System Status
  • A Prototype system has been delivered to LBNL and
    then upgraded (rev C) and delivered to ORNL.
    This system failed during commissioning at ORNL
    (due to unexplained over-voltage) and was
    repaired. It is presently operating at ORNL.
  • Three (3) additional rev C - BCM systems are in
    process for delivery in April to support Linac
    commissioning. We have two LANL PCI cards and are
    building some more.
  • To replace two parts that have been made obsolete
    by the manufacture, requires another art-work
    revision. Our plan is to leave the connectors at
    board end but assure they stay within the PCI
    board spec and incorporate minimal artwork
    changes (present design works).
  • HEBT BCM design is complete. Final drawings are
    in preparation. Ring, and RTBT BCM design is
    underway.
  • Calibrator design for the Ring and RTBT is in
    progress.

14
Elog 1-29-03 ORNL MEBT CommissioningSource Delay
Mode
15
HEBT, Ring, RTBT Current Transformers
16
HEBT BCM ASSEMBLY
17
COMPONENTS INSIDE HEBT BCM ASSEMBLY
18
PRELIMINARY RING/RTBT BCM DESIGN
19
250 us MEBT Pulse During Berkeley Commisssioning
20
Process Variables (2 Channels) -1
  • Chart Data
  • Current chart comfort display (lt256 elements)
  • Averaged over specified time
  • Variables
  • Delay time
  • Time to display
  • Particle count chart (integral of current
    waveshape)
  • Particle count, averaged over the entire
    macro-pulse
  • Particle count, holding average over each
    mini-pulse (particles)
  • array holding raw data for macro-pulse

21
Process Variables (2 Channels) -2
  • Additional PVs
  • Sampling Frequency
  • Gain setting tied to data points
  • Initialize Hardware Control True/False(auto
    reset)
  • PCI Card number
  • Delay time from trigger
  • Number of points to store
  • FIFO Selection
  • Update graphs control ON/OFF
  • Calibration current value
  • Conversion gain
  • Current calibration value
  • Control to permit calibration analysis ON/OFF
  • Delay time
  • Calculation time
  • Droop computation
  • Transformer time constant
  • DC Offset value
  • DC Offset calculation delay time

22
Calibrator Purpose and Requirements
  • Calibrator Purpose
  • Provide a dynamic, on-line measurement of FCT
    droop time constant
  • Confirm the gain of the BCM at various settings
  • MEBT, DTL, CCL, SRF and HEBT (16 Transformers)
  • One range for BCM (0-100 ma)
  • calibration current from 12 bit DAC (up to 20ma)
  • Ring and RTBT (6 Transformers)
  • Will Add 3 BCM ranges. High current driver
    required (up to 4 amp)
  • 350 ma full scale (35 ma from calibrator)
  • 4.2 Amps full scale (420 ma from calibrator)
  • 50 Amps full scale (4 Amps from calibrator)
  • High current driver has a rise time of 1.6 usec,
    too long for good amplitude meas.
  • Plan on two calibration pulse shapes, pulse for
    droop, sine wave for gain
  • Transformer Protection
  • Driver outputs fused to protect from fault
    currents
  • Limited Current from Driver Power Supplies

23
BCM Calibrator Block Diagram
Shows one of two channels
Optical Isolators
Data/Address 12 Bits
To Calibration Winding
12 Bit DAC 125Msps
Memory 64kb/167Mhz
0-10ma
Differential Driver
To calibration Winding (alt.) 0-2 Amp
Timing / Control Logic
Timing/ Control
24
Design Features
  • Basic Design Features
  • A Function Generator using a 12 Bit DAC and a
    64kb memory
  • Two output ports
  • DAC output directly drives lowest current range
  • Current driver drives all other ranges ( 350ma
    to 50 Amp)
  • Isolation from local ground provided by
    opto-isolators and DC/DC converter
  • Transformer Protection
  • Driver outputs fused to protect from fault
    currents
  • Limited Current from Driver Power Supplies
  • Packaging
  • On a multi-layer pcb inside the pc chassis drive
    bay

25
Back-up
26
Xfer response through New 8 Inch BCM Fixture
27
Xfer function to Xfmr Out of new 8 Inch BCM
28
S22 Measurement New 8 Inch BCM Test Apparatus
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