Verilog Synthesis

1
Verilog Synthesis

• Wayne Burleson
• Dept. of Electrical and Computer Engineering
• University of Massachusetts Amherst

2
Objectives

• Get a feel for Verilog
• Hardware Description Language Semantics
• Verilog Syntax
• Features
• How to use Verilog for behavioral (what)
  description
• How to use Verilog for structural (how)
  description
• How to write Verilog for synthesis
• A Simple Example and a Larger Example

3
Readings

• M.H. Smith, ASICs , Addison Wesley Longman,
  1997. We will only cover Chapters 11 and 12.

4
Why HDLs?

• Simulation
• Synthesis
• Documentation

5
How do HDLs differ from conventional programming
languages?

• Electricity
• Parallelism
• Time

6
//Counter Example timescale 1ns/1ns // Set the
units of time to be nanoseconds. module counter
reg clock // Declare a reg data type for the
clock. integer count // Declare an integer
data type for the count. initial // Initialize
things this executes once at t0. begin
clock 0 count 0 // Initialize signals.
340 finish // Finish after 340 time ticks.
end / An always statement to generate the
clock only one statement follows the always so
we don't need a begin and an end. / always 10
clock clock // Delay (10ns) is set to half
the clock cycle. / An always statement to do the
counting this executes at the same time
(concurrently) as the preceding always statement.
/ always begin // Wait here until the clock
goes from 1 to 0. _at_ (negedge clock) //
Now handle the counting. if (count 7)
count 0 else count count 1
display("time ",time," count ", count)
end endmodule
7
gt verilog counter.v VERILOG-XL 2.2.1 Apr 17,
1996 114818 ... Banner information omitted
here... Compiling source file "counter.v" Highest
level modules counter time
20 count 1 time
40 count 2 (... 12 lines
omitted...) time 300 count
7 time 320 count
0 L10 "counter.v" finish at simulation
time 340 223 simulation events CPU time 0.6 secs
to compile 0.2 secs to link 0.0 secs in
simulation End of VERILOG-XL 2.2.1 Apr 17, 1996
114820
8
Verilog Basics from Smith, Chapter 11

• Data types (wire vs. reg)
• Constants
• Buses
• Time and Events
• Common errors (see Problem )

9
More Verilog

• Operators
• Logical (how to deal with x, z)
• Arithmetic (much like C language)

10
Modularity and Hierarchy in Verilog

• Modules
• module holiday_1(sat, sun, weekend)
• input sat, sun output weekend
• assign weekend sat sun
• endmodule

11
Example using Module in Chapter 11.

• http//www-ee.eng.hawaii.edu/msmith/ASICs/HTML/Bo
  ok2/CH11/CH11.04.htm

12
Module vs. Procedure

• Module is a method of building structural
  hierarchy
• Procedure (function) is a method of building
  behavioral hierarchy

13
More Verilog

• Timing
• Control
• Logic-gate Modeling
• Delay Modeling
• Writing to the simulator screen 11.13

14
Parameters

• module Vector_And(Z, A, B)
• parameter CARDINALITY 1
• input CARDINALITY-10 A, B
• output CARDINALITY-10 Z
• wire CARDINALITY-10 Z A B
• Endmodule
• module Four_And_Gates(OutBus, InBusA, InBusB)
• input 30 InBusA, InBusB output 30
  OutBus
• Vector_And (4) My_AND(OutBus, InBusA, InBusB)
  // 4 AND gates
• endmodule

15
More Parameters

• module And_Gates(OutBus, InBusA, InBusB)
• parameter WIDTH 1
• input WIDTH-10 InBusA, InBusB output
  WIDTH-10 OutBus
• Vector_And (WIDTH) My_And(OutBus, InBusA,
  InBusB)
• endmodule
• module Super_Size defparam And_Gates.WIDTH 4
  endmodule

16
Summary of Verilog

• Table from 11.14 http//www-ee.eng.hawaii.edu/ms
  mith/ASICs/HTML/Book2/CH11/CH11.14.htm

17
A Large Example Viterbi Decoder from Smith 11/12

• Just a big state machine
• Note test-bench.
• This was part of an MS thesis that was eventually
  synthesized, fabricated and tested.

18
Problem for Homework 5

• Write behavioral and structural VERILOG for hex
  digit accumulator
• Hard-wire the 4 least significant hex digits of
  your student number.

19
Verilog for Synthesis

• Chapter 12.5 in Smith
• Synthesizers can only deal with a small sub-set
  of the Verilog language.
• You need to be very precise in how you use
  Verilog in order for the logic synthesis to map
  to the correct hardware.