Shared Memory Consistency

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Shared Memory Consistency

• Submitted by
• Rakhi Anand

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Introduction

• Shared Memory consistency is defined as a read
  should return a value of last write to same
  memory location.

P1
P2
P3
Memory
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Example

• Initially A flag 0
• P1 P2
• A1 while(flag 1)
• flag1 print A

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Sequential Consistency

• Result of an execution is in sequential order for
  all processors
• Maintaining program order among operations
• Maintaining program order for all operations
  (atomicity)

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Program order example

• flag1 flag2 0
• P1 P2
• flag11 flag21
• If (flag20) If (flag10)
• Critical section Critical section

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Atomicity example

• Initially A B 0
• P1 P2 P3
• A1
• if(A1)
• B1
• if(B1)
• register1A

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Implementation

• Architecture without caches
• Write Buffers with read bypassing
• Overlapping writes
• Non blocking reads

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Write Buffers with read bypassing
P2 Flag21 if (Flag10) Critical section
P1 Flag11 if (Flag20) Critical section
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Overlapping writes
Read Data t3 Read Head t2
P2 While(Head1) Data
P1 Data2000 Head1
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Nonblocking Reads
Write Head t3 Write Data t2
General Interconnect
P2 While(Head1) Data
P1 Data2000 Head1
Memory
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Implementation

• Architecture with caches
• Cache coherence Protocols
• Detecting write completion
• Maintaining write atomicity

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Cache coherence Protocols

• A write must eventually be visible to all
  processors
• Writes to same location must appear in same order
  for all processors.

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Detecting write completion

• Acknowledge of an invalidate or update

P1 Data2000 Head1
P2 While(Head1) Data
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Maintaining write atomicity

• Writes to same location should be serialized
• Initially A B C 0
• P1 P2 P3 P4
• A1 A2 while(B!1) while(B!1)
• B1 C1 while(C!1) while(C!1)
• register1A register2A

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Maintaining write atomicity

• Prohibiting a read from returning a newly written
  value until all cached copies have
  acknowledgement receipts
• Initially AB1
• P1 P2 P3
• A1
• if(A1)
• B1
• if (B1)
• register1A

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Compilers

• Hardware techniques
• Compiler techniques

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Hardware techniques

• Prefetching ownership write any write operation
  that is delayed due to program order requirement
• Servicing read operations that are delayed due to
  program order requirement

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Compiler techniques

• To detect when memory operations can be reordered
  without violating sequential consistency.

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Relaxed Memory models

• Relax program order requirement
• Write to following read (W-gtR)
• Between two writes (W-gtW)
• Read to following read or write (R-gtRW)
• Write atomicity requirement
• Read returns value before it is made globally
  visible. (ROth.-gtWEarly)

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Relaxed Memory models

• Relax both program order and write atomicity
  (ROwn-gtWEarly)
• A processor can read the value of its own write
  before the write is visible to other processors.

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Relax program order requirement

• Write to following read
• IBM 370
• Serialization instructions
• TSO (Total Store Ordering)
• RMW
• PC (Processor Consistency Model)
• RMW

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Example

• Initially A Flag1 Flag2 0
• P1 P2
• Flag11 Flag21
• A1 A2
• register1A register3A
• register2Flag2 register4Flag1
• Result register11, register32,
• register2register40

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Example.

• Initially A B 0
• P1 P2 P3
• A1
• if(A1)
• B1
• if(B1)
• register1A

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Relax program order requirement

• Between two writes or write to read
• PSO (Partial Store Ordering Model)
• Writes are pipelined or overlapped and safety net
  used is RMW, STBAR

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Relaxing all program orders

• RCsc
• Release, acquire, RMW
• RCpc
• Release, acquire, RMW
• Alpha
• MB, WMB
• RMO
• MEMBARS
• PowerPC
• SYNC

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References

• S.V. Adve, Kourosh Gharachorloo Shared Memory
  Consistency Models A Tutorial
• S.V. Adve, Designing Memory Consistency Models
  for shared Memory Multi processors
• Tracy Harton, Sarita Adve, Evaluation of shared
  memory Models with ILP Processors
• http//parasol.tamu.edu/rwerger
• Thanks to Dr. Chapman