CLOCK DISTRIBUTION

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CLOCK DISTRIBUTION

• Shobha Vasudevan

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The clock distribution problem

• Large Chip Area
• Different flop densities
• Non-uniform distribution of flops
• All flops need to get clock signal at the same
  time
• Power budget
• Clock routinghard problem

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Stages of Clock design

• Global Routing (matched impedance)
• Impedance matching at every block
• Local Routing within every block

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Iterations of the clock tree

• First iteration on floorplan

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Second iteration
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Assumptions made in initial iterations

• Flop Distribution not decided
• LCB placement and distribution not decided
• LCBs placed at the entry point of H in block
• Matched Impedance at every entry point of global
  tree in block

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Third Iteration Impedance Matching

• Assumptions
• LCBs placed on edge of blocks
• Internal Routing of clock from LCBs to blocks
• Uniform distribution of flops in random logic
  blocks (Control, System and Exceptions)

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LCB placements and distribution
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Directives in clock tree design

• Zero or minimal skew to LCBs
• Skew budget 20 ps
• No routing over arrays (Caches and MMUs)
• Extensive wiring over Control block
• Routing through the center for uniformly
  distributed flop regions.

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Directives in clock tree design

• M5 for horizontal lines
• M6 for vertical lines
• Gated flops in the LSU, MAC and GPR region

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Clock Tree DesignBinary Tree

• Uniform distribution of load
• Division into clusters of 8-9 LCBs
• Binary tree with each cluster as a leaf node
• Levels of binary tree as equivalent capacitance
  points
• Unbalanced branches of tree balanced by adding
  equivalent capacitance
• Balancing capacitanceExtra wire routing

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Clock tree designBinary tree
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Clock tree design
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Routing issues

• GCBs placed at root and ends of pink and blue
  lines (1641)
• Equivalent capacitances maintained at every level
  of the tree
• Wire length and thickness varied to match
  capacitance

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Hspice simulation

• Capacitance and resistance of M5 and M6 factored
  for every horizontal and vertical branch
• Balancing capacitance added
• Skew found for all 47 leaf nodes

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Waveforms
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Hspice resultsGlobal Skew
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Hspice simulation results
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Skew introducing factors

• Different capacitances at the leaf nodes (8 LCBs
  or 9 LCBs)
• M5 and M6 not accounted for in the routing
• Discrepancies in length of wire

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The BST-DME algorithm

• Academic tool (Andrew Kahn, UCLA)
• Uses Divide-Merge-Embed Algorithm
• Calculates minimum wire length for bounded skew
• Accepts coordinates of LCBs and their
  capacitances
• Baseline Metric

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Tree coordinates produced by BST
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To be done

• Precharge of Caches not routed
• Plan
• Add capacitive load of precharge LCBs to the
  corresponding leaf nodes
• Route extra wire for the other branches to
  balance load
• Timeline May 1st