VLSI System Design Methodologies

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VLSI System Design Methodologies

• Md. Shabiul Islam
• Lecture No 7
• MULTIMEDIA UNIVERSITY

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Topics

• CAD systems.
• Simulation.
• Placement and routing.
• Layout analysis.

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Introduction

• A modern CAD system is built from several million
  lines of code, so it isnt reasonable to assume
  that a designer will understand every nuance of
  each tool.
• Any tool must operate on an abstraction logic
  optimizers, for example, have almost no knowledge
  of layout, except perhaps for parasitic
  capacitance estimates.

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• The properties of the tools model are intimately
  linked to the algorithm used- we select a model
  that can be efficiently solved.
• CAD algorithms are carefully chosen to be
  efficient because chip design problems can grow
  to be extremely large, requiring hours or days of
  CPU time to solve.

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CAD systems

• Tools arent very useful if they dont talk to
  each other.
• Design interchange languages
• VHDL (TM), Verilog (TM) (function and structure)
• EDIF (netlists)
• GDS, CIF (masks).

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CAD tool interactions
xlate a
tool 1
tool 2
tool 1
tool 2
xlate b
xlate c
database
xlate d
xlate e
tool 3
tool 4
tool 3
tool 4
database (hub-and-spoke)
translator
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Back annotation

• Design data generated at one stage should be kept
  for later checking. One important function of
  integrated CAD systems is Back-annotation-the
  amendment of a description, usually a circuit or
  gate net list, with new information.
• For example, simulation and delay analysis
  performed before layout design.

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Back annotation

• Often want to iteratively improve design.
• Back annotation updates a more-abstract design
  with information from later design stages.
• Example annotate logic schematic with extracted
  parasitic Rs and Cs.
• Back annotation requires tools to know more about
  each other.

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Event-driven simulation

• The behavior of digital systems presents two
  major opportunities to simplify simulation.
  First, digital circuits compute only discrete
  values ( at least, when they work properly).
• Second, logic values may changes relatively
  infrequently, and outputs change only when input
  change.

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Event-driven simulation

• Event-driven simulation is designed for digital
  circuit characteristics
• small number of signal values
• relatively sparse activity over time.
• Event-driven simulators try to update only those
  signals which change in order to reduce CPU time
  requirements.

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Event-driven simulator structure

• Virtually all digital logic simulators are
  event-driven, they evaluate a component only when
  an event occurs on its inputs.An event is a
  change in a signal value.
• A timewheel is a queue of events.
• Simulator traces structure of circuit to
  determine causality of eventsevent at input of
  one gate may cause new event at gates output.

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Event-driven simulation example
A
C
D
B
logic network
behavior
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Event-driven simulation example, contd

• Events at primary inputs
• A changes at t1
• B changes at t2.
• Immediate causality
• C changes at t3 when both inputs to NOR are 0.
• Event propagation
• D changes at t4.

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Delay models

• Unit-delay simulators assume that each component
  has a one-unit delay. Model function but not
  performance.
• Variable-delay simulators allow each component to
  have its own delay. Accuracy of performance
  estimates from variable-delay simulators depends
  on how well circuits can be extracted to digital
  model.

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Switch simulation

• Logic gate models for simulation are important,
  but they may give misleading simulation results
  for systems built from MOS transistors. Even if
  we reduce the transistor to an ideal switch, a
  undirectional logic gate can not model charge
  sharing, which is a result of the
  bidirectionality of MOS transistors.

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Switch simulation

• Special type of event-driven simulation optimized
  for MOS transistors.
• Treats transistor as switch. Takes capacitance
  into account to model charge sharing, etc.
• Can also be enhanced to model transistor as
  resistive switch.

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Switch simulation example
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Switch simulation example, contd

• Node g may be connected to either power supply,
  but signals on that node are terminated by gate
  of transistor.
• To solve for values of a and b nodes, must first
  solve for value of g node.
• If g1, then ab.
• If g0, other parts of circuit determine a and b
  independently.

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Switch simulation and charge sharing

• Closed transistor connects source and drain
  nodes. Want to determine voltages of source/drain
  nodes taking into account capacitance.
• Capacitance determines node size. Use size of
  connected nodes to determine new value of nodes.
• Result may be X (unknown).

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Layout synthesis

• Layout is among the most tedious of design tasks,
  so it is natural to want to automate layout
  design as much as possible.
• Automatic layout methods vary in the quality of
  the layout produced (both in chip area and
  delay), in the degree of automation, and the
  total manufacturing cost of the design.

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Layout synthesis

• Two critical phases of layout design
• placement of components on the chip
• routing of wires between components.
• Placement and routing interact, but separating
  layout design into phases helps us understand the
  problem and find good solutions.

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Placement metrics

• Quality metrics for layout
• area
• delay.
• Area and delay deterined in part by wiring.
• How do we judge a placement without wiring?
  Estimate wire length without actually performing
  routing.

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Wire length as a quality metric
bad placement
good placement
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Wire length measures

• Estimate wire length by distance between
  components.
• Possible distance measures
• Euclidean distance (sqrt(x2 y2))
• Manhattan distance (x y).
• Multi-point nets must be broken up into trees for
  good estimates.

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Placement techniques

• Can construct an initial solution, improve an
  existing solution.
• Pairwise interchange is a simple improvement
  metric
• Interchange a pair, keep the swap if it helps
  wire length.
• Heuristic determines which two components to swap.

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Placement by partitioning

• Works well for components of fairly uniform size.
• Partition netlist to minimize total wire length
  using min-cut criterion.
• Partitioning may be interpreted as 1-D or 2-D
  layout.

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Min-cut bisecting partitioning
B
A
C
D
partition 1
partition 2
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Min-cut bisecting partitioning, contd

• Swapping A and B
• B drags 1 net
• A drags 3 nets
• total cut increase 4 nets.
• Conclusion probably not a good swap, but must be
  compared with other pairs.

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Kernighan-Lin algorithm

• Compute min cut criterion
• count total net cut change.
• Algorithm exchanges sets of nodes to perform
  hill-climbingfinding improvements where no
  single swap will improve the cut.
• Recursively subdivide to determine placement
  detail.

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Simulated annealing

• Powerful but CPU-intensive optimization
  technique.
• Analogy to annealing of metals
• temperature determines probability of a component
  jumping position
• probabilistically accept moves.
• start at high temperature, cool to lower
  temperature to try to reach good placement.

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Routing

• Major phases in routing
• global routing assigns nets to routing areas
• detailed routing designs the routing areas.
• Net ordering is a major problem. Order in whch
  nets are routed determines quality fo result. Net
  ordering is a heuristic.

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Maze routing

• Will find shortest path for a single wire, if
  such a path exists.
• Two phases
• Label nodes with distance, radiating from source.
• Use distances to trace from sink to source,
  choosing a path that always decreases distance to
  source.

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Maze routing example
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Detailed routing

• Dogleg router breaks net into multiple segments
  as needed.
• Try to minimize number of dogleg segments per net
  to minimize congestion for future nets.
• One good heuristicuse left-edge criterion on
  each dogleg segment to fill up the channel.

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Rivest-Fiduccia channel router

• Routes from left to right. Assigns all nets that
  cross the current column to tracks.
• Heuristics
• Make connections to pins.
• Add jogs to put multi-track net into one track.
• Add jogs to reduce distance in multi-track nets.
• Add jogs to move net toward next pin.
• Add tracks when necessary.

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YACR2

• Tries to minimize number of vias as well as
  number of tracks.
• Temporarily satisfies vertical constraints by
  adding blank space between pins.
• Eliminates blank space ater by adding jobs.
• May route in both directions on same layer.

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Layout analysis

• Test design rules using Boolean combinations of
  masks, grow/shrink.

M2
M1
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Scan line algorithm

• Mark each edge of polygon with direction.
• Sweep scan line across layout.
• At each point on scan line, count number of
  left-hand and right-hand edges to determine what
  rectangle that point is in.

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Scan line algorithm example
M2
M1