International Technology Roadmap for Semiconductors

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International Technology Roadmap for
Semiconductors 2006 ITRS Update/ORTC
Product Models Status Including 1Q06 SIA/SICAS
Industry Technology Capacity Demand Analysis For
Public 07/12/06 Conference SEMICON / San
Francisco, CA (Draft Rev 0, 06/30/06)
Semiconductor Industry Association /
Semiconductor Industry Capacity Statistics
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2005 ITRS Executive Summary Fig 5
Source 2005 ITRS Document online at
http//www.itrs.net/Links/2005ITRS/Home2005.htm
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ORTC Overview 2006 Update ITRS - Unchanged

• One standard TWG table technology trend header
• Presently continue to use DRAM stagger-contacted
  M1 as typical industry lithography driver
• Transitioned to product-oriented technology trend
  drivers and cycles
• ORTC Table 1a,b - MPU/ASIC M1 Half-Pitch Trend
• Stagger-contacted, same as DRAM
• 2.5-year Technology Cycle (.5x/5yrs)
• 180nm/2000 90nm/2005 45nm/2010(equal DRAM)
• Then continue on a 3-year Technology Cycle,
  equal to DRAM 2010-2020
• ORTC Table 1a,b - STRJ Flash Poly (Un-contacted
  dense lines)
• 2-year Technology Cycle (0.5x/4yrs)
• 180nm/2000 130nm/2002 90nm/2004 65nm/2006
• Then 3-year Technology Cycle 1 year ahead of
  DRAM 06-20
• ORTC Table 1a,b MPU/ASIC Printed Gate Length
  per FEP and Litho TWG ratio relationship to Final
  Physical Gate Length - UNCHANGED from the 2005
  ITRS targets (3-year cycle after 2005)
• TWG table Product-specific technology trend
  driver header items are added to individual TWG
  tables from ORTC Table 1ab
• Chip Size Models are connected to proposals and
  historical trends, incl. new Flash Model
• Function Size Logic Gate SRAM Cell Dram Cell
  Flash Cell (SLC, MLC)
• Functions/Chip Flash DRAM High Performance
  (hp) MPU Cost Perf. (cp) MPU
• Chip Size hp MPU cp MPU DRAM Flash

Note Cycle time to 0.5x linear scaling
every two cycle periods 0.71x/ cycle
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Summary

• DRAM Model stagger-contacted M1 is unchanged from
  2005 ITRS (3-year cycle after 2004)
• MPU M1 stagger-contact half-pitch is on a
  2.5-year cycle through 2010/45nm, then 3-year
  cycle
• Flash Model un-contacted poly half-pitch
  continues on 2-year cycle to 1 year ahead of
  DRAM (contacted) in 2006, then 3-year cycle
• Printed MPU/ASIC Gate Length set by FEP and Litho
  TWGs ratio agreement, but Physical GL targets
  remain unchanged and on 3-year cycle beginning
  2005
• Industry Technology Capacity Demand (SICAS) still
  on 2-year cycle
• Total MOS Capacity is growing 11 CAGR (SICAS),
  and 300mm Capacity Demand has ramped to 22 of
  Total MOS
• Historical chip size models connected to
  Product scaling rate models, and include design
  factors, function size, and array efficiency
  targets
• Average industry product Moores Law met or
  exceeded throughout 2005-2020 ITRS timeframe
• ITRS Cycle definition time to .5x linear
  scaling every two cycle periods

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Backup
Source 2005 ITRS Document online at
http//www.itrs.net/Links/2005ITRS/Home2005.htm
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ORTC Table 1a,b (Near, Long Term)
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ORTC DRAM Flash Prod Table 1c (Near Term)
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ORTC DRAM Flash Prod Table 1d (Long Term)
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ORTC Table DRAM Intro 1e,f (Near, Long Term)
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ORTC MPU cp Table 1g (Near Term)
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ORTC MPU cp Table 1h (Long Term)
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ORTC MPU/ASIC hp Table 1i (Near Term)
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ORTC MPU/ASIC hp Table 1j (Long Term)